Packaging structure and packaging method of semiconductor chip

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a packaging structure and a packaging method of a semiconductor chip. The packaging structure of the semiconductor chip comprises a wafer, an insulation structure and a conductive part. A functional area and electrodes are arranged on the first surface of the wafer, the electrodes are distributed at intervals in the circumferential direction of the functional area, and the side walls, away from the functional area, of the electrodes are obliquely arranged; the insulating structure covers the first surface, one side of the insulating structure facing the wafer is provided with an accommodating space, the functional area is arranged between the accommodating space and the first surface, and the side wall of the insulating structure is obliquely arranged and is coplanar with the side wall of the electrode away from the functional area to form a cutting slope inclining towards the middle of the insulating structure; and the conductive part covers the cutting inclined surface and is electrically connected with the electrode, and the conductive part extends to the end surface, opposite to the wafer, of the insulating structure along the outer contour of the insulating structure. According to the invention, the conductive part is of a planar structure on the side wall of the chip, so that the number of inflection points on the conductive part is reduced, and the structural strength and durability of the conductive part are ensured.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor chip packaging structure and packaging method. Background technique [0002] With the rapid development of the personal consumer electronics industry, smart devices such as notebook computers are becoming more and more portable and functional. Therefore, improving the reliability of the chip packaging structure inside the smart device is also an important development direction. In the prior art, the chip package structure includes a wafer and an insulating structure covering the wafer. In the packaging structure of one type of chip, the side wall of the insulating structure is covered with a metal wire layer, which conducts the electrical signal of the electrode on the wafer to the upper surface of the insulating structure, so as to facilitate connection with the external conductive structure. The electrodes are usually arranged at the edge of th...

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Problems solved by technology

However, the insulation structure usually includes two layers of insulation layers, and the coverage area of ​​the two layers of insulation layers decreases from bottom to top, that is, a stepped surface is generated at the side wall of the insulation structure, so that the metal wire layer covering the side wall of the insulation structure has an inflection point, and at the inflection point Larger resistance increases the heat generation on the metal wire layer. Excessive heat reduces the reliability of destroying the chip packaging structure. It also increases the location of stress concentration on the metal wire layer and increases the possibility of metal wire layer breakage. , affecting the structural strength and durability of the metal wire layer

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