Line speed changing method and system based on Rocket IO high-speed interface

Abstract

The invention provides a line speed changing method and system based on a Rocket IO high-speed interface. The method is applied to a Rocket IO high-speed interface line speed changing system; the Rocket IO high-speed interface line speed changing system comprises a Rocket IO interface board, a PCIe backboard, and amain control board, wherein the Rocket IO interface board is connected with a PCIe mainboard, and the PCIe backboard is connected with the main control board; the installation of the Rocket IO interface board is a PCB adopting a Xilinx FPGA. According to the line speed changing method based on the Rocket IO high-speed interface, by configuring a very simple register list, the Rocket IO line speed changing method is realized; a register list scheme with extremely simple configuration is adopted, a Rocket IO variable line speed changing scheme is realized, and other interfaces do not need to be added, so that the method has relatively high universality.

Description

technical field [0001] The invention relates to the field of data storage technology and high-speed data transmission technology, in particular to a method and system for changing wire speed based on a RocketIO high-speed interface. Background technique [0002] In the field of information storage, the computer storage structure usually adopts the PCIe bus structure. In the face of various practical business needs, we need to transfer various business data to the storage medium through the optical fiber interface. storage etc. The data transfer process from the optical fiber interface to the PCIe interface only involves the interface conversion task, and is generally designed as an interface board separately to meet the requirements of interface conversion and board replacement. [0003] Xilinx's RocketIO high-speed serial transceiver interface is a high-speed transceiver module integrated in Virtex2 pro and above series FPGAs that can reach Gb / s transmission speed. It is ...

AI Technical Summary

Problems solved by technology

However, limited to SOC chips, non-SOC chips are not available

[0012] 3) Mode 3, usually first convert low-speed interfaces such as I2C, SPI, UART serial ports to AXI-lite interface, and then convert to DRP interface timing. This method is also more flexible and has a certain market, but low-speed interfaces must be added. configuration interface

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