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a chip

A chip and pin technology, applied in the field of chips, can solve the problems of waste and limitation of chip area, and achieve the effect of reducing wafer area and cost

Active Publication Date: 2022-07-05
广芯微电子(广州)股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The chip area of ​​the prior art solution is mainly limited by the area of ​​the quadrilateral surrounded by the input and output pins of the chip, that is, figure 1 The area of ​​X0*Y0 in the middle, but if the total area consumed by the core logic of the chip is less than the area of ​​X0*Y0 under the condition that the function can be realized, the chip area will be wasted

Method used

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Experimental program
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Effect test

Embodiment 1

[0025] Refer to the attached figure 2 and attached Image 6 , the invention discloses a chip, which includes core logic and input and output pins, and input and output pins are arranged around the core logic; the input and output pins include: a first circle of input and output pins and a second circle of input and output pins Output pins; the core logic is arranged in the first circle of input and output pins, and the first circle of input and output pins is arranged in the second circle of input and output pins.

[0026] Refer to appendix 1 and appendix figure 2 , it can be seen that the arrangement of the input and output pins of the first circle and the input and output pins of the second circle of the present invention makes X1

[0027] In the technical solution of the present invention, those skilled in the art know that the chip has a large number of input and output p...

Embodiment 2

[0036] On the basis of Embodiment 1, the present invention also discloses a chip, which includes core logic and input and output pins, and input and output pins are arranged around the core logic; the input and output pins include: a first circle of input and output pins Output pins, input and output pins of the second circle and input and output pins of the third circle; the core logic is arranged in the input and output pins of the first circle, and the input and output pins of the first circle are arranged in the input and output pins of the second circle In the output pins, the input and output pins of the second circle are arranged in the input and output pins of the third circle.

[0037]Combined with the connection scheme of the power ground pins in implementation 1, the power ground pins of the input and output pins of the first circle, the power ground pins of the input and output pins of the second circle, and the power ground pins of the input and output pins of the ...

Embodiment 3

[0042] On the basis of implementation 1 or implementation 2, refer to the appendix Figure 7 , those skilled in the art can set the number and position of the input and output pins of the first circle as needed, and do not necessarily completely surround the core logic; those skilled in the art can set the number and position of the input and output pins of the second circle as needed. The number and position of the pins do not necessarily completely surround the first circle of input and output pins.

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Abstract

The invention belongs to the technical field of chips, and discloses a chip, comprising core logic and input and output pins, and input and output pins are arranged around the core logic; the input and output pins include: a first circle of input and output pins and The second circle of input and output pins; the core logic is arranged in the first circle of input and output pins, and the first circle of input and output pins is arranged in the second circle of input and output pins. Beneficial effects: The first circle of input and output pins and the second circle of input and output pins provided by the present invention can effectively reduce the wafer area required for the core logic of the chip, thereby reducing the cost of the chip and making the product more competitive .

Description

technical field [0001] The present invention relates to the field of chip technology, in particular to a chip. Background technique [0002] The cost of chips has an important impact on the competitiveness of related products. If cheaper chips can be used to achieve the same performance and reduce product costs, the competitiveness of products can be effectively improved. At present, there are many factors that affect the cost of a single chip, and the main consideration in the implementation stage of chip physical design is to save the chip area. The smaller the chip area, the more chips can be cut out from a single wafer (wafer) The lower the cost. [0003] For chips with more input and output pins, the existing technical solutions are as follows figure 1 , the input and output pins of the chip are arranged adjacent to each other around the chip. figure 1 The strip shape around the middle is the input and output pins, and the units that do not include the input and outp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/394G06F113/18
CPCG06F30/394G06F2113/18
Inventor 王锐关娜王亚波李建军莫军
Owner 广芯微电子(广州)股份有限公司
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