Clock control circuit

Abstract

The invention discloses a clock control circuit, which comprises a first phase-locked loop, a second phase-locked loop and a third phase-locked loop, wherein the input end of the first phase-locked loop is connected with a first multiplexer; one end of the first phase-locked loop is connected with the output end of the second phase-locked loop, and an output signal of the first phase-locked loop is used as a reference signal of the second phase-locked loop; and the output end of the second phase-locked loop is connected with the phase shifter and the clock frequency divider and is used for controlling phase output after frequency division of the clock. A first PLL (Phase Locked Loop) in the clock control circuit is connected with a loop filter and a voltage-controlled crystal oscillator to form a PLL loop, so that a stable filtering clock can be output on the first PLL loop, and the stably output filtering clock is input into a second PLL loop to obtain an accurate jitter clock.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a clock control circuit. Background technique [0002] At present, the clock control circuit with a single PLL (Phase Locked Loop) structure is susceptible to random clock jitter and periodic clock jitter due to interference from IC chips, switching power supply noise, data or clock lines, making the overall clock quality poor and affecting system performance. Contents of the invention [0003] One object of the present invention is to provide a clock control circuit, the clock control circuit adopts a dual PLL structure, wherein the output signal of one PLL is used as the input signal of the other PLL, so that the clock jitter can be effectively controlled and the clock quality can be improved. [0004] Another object of the present invention is to provide a clock control circuit. The first PLL in the clock control circuit is connected with a loop filter and a voltage-controlled crysta...

AI Technical Summary

Problems solved by technology

[0002] At present, the clock control circuit with a single PLL (Phase Locked Loop) structure is susceptible to interference from IC chips, switching power supply noise, data or clock lines, resulting in random clock jitter and periodic clock jitter, making the overall clock quality poor and affecting system performance.

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