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Central processing unit and manufacturing method thereof

A technology of central processing unit and buffer, applied in the semiconductor field, can solve problems such as poor CPU performance, achieve the effects of good performance, increase usage, and reduce distance

Active Publication Date: 2021-07-09
YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, limited by the capacity and volume of SRAM, the performance of CPU is not good

Method used

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  • Central processing unit and manufacturing method thereof
  • Central processing unit and manufacturing method thereof
  • Central processing unit and manufacturing method thereof

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Embodiment Construction

[0038] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the specific technical solutions of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present invention.

[0039] Due to the huge difference in storage speed and cost of different storage technologies, in order to access data efficiently, in the computer storage system, the most commonly used data is placed on the storage device with a fast reading and storage speed, and the infrequently used data is placed on the storage device with a fast reading and storage speed. on slow storage devices. A memory system is a hierarchy of storage devices with varying capacities, costs, and access times. Such as Figure 1a As shown, the buffer memory, main memory, and disk storage capacity of the CPU arranged from left to right are getting larger and larger, but the access speed is getting slower and slower. F...

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Abstract

The embodiment of the invention provides a central processing unit (CPU) and a manufacturing method thereof. The CPU comprises at least one kernel, a multi-stage buffer in signal connection with the kernel; wherein the buffers of different levels in the multi-level buffer comprise storage unit layers of different layers in the phase change memory; the phase change memory comprises a plurality of stacked memory unit layers; the storage unit layer comprises a plurality of storage units. Different levels of caches in the multi-level caches in the CPU adopt different layers of storage unit layers in the same phase change memory; wherein the final size of the CPU can be obviously reduced due to the smaller size of the phase change memory, so that the delay between a CPU kernel and each level of buffer is reduced, and more data can be exchanged through the multi-level buffer due to the higher capacity of the phase change memory, so that the use amount of the cached data is increased. The CPU provided by the embodiment of the invention has better performance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a central processing unit (CPU, Central Processing Unit) and a manufacturing method thereof. Background technique [0002] In order to solve the contradiction between CPU computing speed and memory reading and writing speed, a CPU register has appeared. The CPU cache is a temporary data exchange between the CPU core and the memory. Its capacity is smaller than that of the memory, but its exchange speed is faster than that of the memory. The operating speed and capacity of the CPU cache are directly related to the type of memory used in the CPU cache. [0003] In the related art, the CPU register generally includes multiple levels, and the multi-level CPU register generally adopts Static Random-Access Memory (SRAM, Static Random-Access Memory). However, limited by the capacity and volume of the SRAM, the performance of the CPU is poor. Contents of the invention [0004...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C13/00H01L45/00
CPCG11C13/0004H10N70/801H10N70/231Y02D10/00
Inventor 刘峻
Owner YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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