Manufacturing method of separation gate power MOSFET device

Abstract

The invention provides a manufacturing method of a separation gate power MOSFET device, which comprises the following steps of: after a dielectric layer between a control gate and a separation gate is formed, depositing or thermally growing a sacrificial oxide layer, depositing silicon nitride to fill the whole groove structure, and separating the silicon nitride from a silicon layer in an MESA region through the sacrificial oxide layer; after etching the silicon nitride, taking the silicon nitride reserved in the groove as a shielding layer for etching the oxide layer; etching the oxide layer until the interface of the oxide layer is higher than the upper interface of the stepped separation gate, and then etching the residual silicon nitride; and depositing polycrystalline silicon and performing back etching to form a control gate electrode. According to the device structure prepared by the invention, the lower half part of the control gate is relatively narrow, so that the gate-source capacitance Cgs can be greatly reduced, and meanwhile, the upper half part of the control gate increases the cross sectional area of gate current flowing, so that the gate resistance is reduced and the targets of high switching speed and low switching loss are achieved on the premise of ensuring that the gate-source capacitance Cgs and gate charge Qg are not degraded.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and more particularly, relates to a manufacturing method of a split gate power MOSFET device. Background technique [0002] With the continuous development of new fields in the electronic information industry, power semiconductor devices have also ushered in a new round of development peaks. At the same time, higher requirements have been placed on the performance of power MOSFETs. Lower switching losses and higher working efficiency have become the key points of power devices. development trend. The advantages of power VDMOS with high frequency and low power consumption are gradually manifested, especially in power management and other fields. The split gate power MOSFET device structure developed based on the Trench MOSFET device utilizes the split gate electrode to shield the capacitive coupling between the control gate electrode and the epitaxial layer to reduce the gate-drain parasit...

AI Technical Summary

Problems solved by technology

However, split-gate power MOSFET devices introduce parasitic capacitances associated with the split-gate electrode: the capacitance Cds between the drain and the split-gate electrode and the capacitance Cgs between the gate and the split-gate electrode, and the increased parasitic capacitance offsets to some extent The advantages of split-gate MOSFET devices to reduce gate-to-drain capacitance Cgd

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