A method for preparing and packaging multiple chips at the same time

A chip and chip array technology, applied in the field of simultaneous preparation and packaging of multiple chips, can solve problems such as the increase in the cost of SiC material devices, increase process complexity, reduce design complexity and preparation process complexity, and improve product application value. Effect

Active Publication Date: 2022-07-22
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the extremely small size will also increase the cost of SiC material devices, mainly including the complexity of chip dicing and the complexity of chip extraction, etc.

Method used

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  • A method for preparing and packaging multiple chips at the same time
  • A method for preparing and packaging multiple chips at the same time
  • A method for preparing and packaging multiple chips at the same time

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Embodiment

[0036] The invention discloses a method for preparing, packaging and using multiple chips at the same time, which is mainly suitable for small-volume, high-power silicon carbide devices. The application situation is mainly for array units. The invention is mainly but not limited to the following Happening:

[0037] In the case of using in module A, when multiple identical low-current chips are required, the chips in the array can be used in different positions of the module through an external circuit;

[0038] B In circuits that require high reliability, since the chips in the array unit are tape-outs of the same batch and the same chip, the device consistency is high, and the devices can back up each other;

[0039] C Even only from the perspective of cost reduction, the different chips of the array unit are connected in parallel and independent of each other. Through testing and screening, the waste chips in the array unit can be eliminated without wire bonding (or after wi...

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PUM

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Abstract

The invention discloses a method for preparing and encapsulating multiple chips at the same time. The method includes: optimization of the layout design of the wafer where the device chip is located; optimization of the specific structure design of the device chip; the original micromachining process and difficulty remain unchanged; And the use process of packaging is simplified, and the total fabrication cost of the device is reduced. Through design optimization, the invention reduces the workload of the device in the stages of testing, dicing and picking, so as to achieve the purpose of reducing costs and improving product competitiveness; especially for devices with small volume and high power such as silicon carbide-based devices potential application value.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a method for preparing and packaging multiple chips at the same time. Background technique [0002] SiC material has large forbidden band width, high breakdown electric field, high saturation drift speed and high thermal conductivity. Therefore, SiC materials can often achieve the same electrical properties as other semiconductor materials (especially silicon) in a smaller volume. However, the extremely small size will also increase the cost of SiC material devices, mainly including the complexity of chip cutting and the complexity of chip access. [0003] In particular, silicon carbide has the advantage of making high-voltage devices. For chips of high-voltage devices, a terminal structure with a certain width is required to control the fringing electric field. This part of the area is positively related to the voltage, so it accounts for a large proportion in low-current ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L21/56H01L25/07H01L29/06
CPCH01L25/50H01L21/561H01L25/07H01L29/0623H01L29/0615H01L29/0684
Inventor 陈允峰李士颜刘昊陈谷然黄润华柏松
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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