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Semiconductor packaging method

A packaging method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of restricting the development of panel size enlargement, difficulty in locating the precise position of bare chips, and the influence of wiring technology, etc., to achieve guaranteed Success rate and product yield, the effect of meeting precision production requirements

Active Publication Date: 2022-07-01
SIPLP MICROELECTRONICS CHONGQING CO LTD
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The change of the position of the die on the panel makes it difficult to locate the precise position of the die on the panel in the subsequent wiring process, which has a great impact on the wiring process and even makes it difficult to carry out the wiring process.
[0005] Solving the problem of positioning the die has become one of the keys to the entire process. The problem of positioning the die even limits the development of panel size enlargement and becomes a technical barrier in large-size panel packaging.

Method used

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  • Semiconductor packaging method
  • Semiconductor packaging method
  • Semiconductor packaging method

Examples

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Embodiment Construction

[0033] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

[0034] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention belongs. Words like "a" or "an" used in the specificat...

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Abstract

The present application provides a semiconductor packaging method, which includes: forming an adhesive layer on a carrier board, dividing a plurality of arrangement areas and blank areas on the adhesive layer, and setting the blank areas around the arrangement areas; setting positioning on the blank areas The positioning hole is located in the outer peripheral area of ​​the arrangement area; according to the position of the positioning hole, the chip to be packaged is mounted in the arrangement area; an encapsulation layer is formed, the encapsulation layer covers the adhesive layer, and the encapsulation layer At least a part of the positioning holes is filled in the positioning holes to form positioning bumps, and the encapsulation layer is used to encapsulate the chips to be packaged. In the present application, positioning holes are provided to locate the precise position of the patch to be packaged on the carrier board, which can ensure the mounting accuracy in the chip mounting process; the positioning protrusions formed in the positioning holes can be used in the subsequent re-wiring process. The precise positioning identifies the arrangement position of each chip to be packaged, and achieves the function of precise positioning again.

Description

technical field [0001] The present application relates to the technical field of semiconductors, and in particular, to a semiconductor packaging method. Background technique [0002] In the panel-level packaging process, the precise positioning of the die on the panel has always been a key factor in panel packaging. The precise positioning of the die on the panel has a great impact on the wiring process and will affect the yield of the product. [0003] Especially in the large-scale panel packaging process, due to the large curing area of ​​the plastic sealing resin during the plastic sealing process, the degree of curing shrinkage is correspondingly large. During the heating and cooling process, a large amount of stress is accumulated inside the material, which causes the warpage of the molded product after molding. Both the curing shrinkage of the panel resin and the warpage of the panel will cause the positioning position of the die on the panel to change. [0004] The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56
CPCH01L21/561H01L2224/18H01L2224/96
Inventor 周辉星
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD
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