Cache replacement method and device based on energy consumption characteristics of MLC STT-RAM

Abstract

The invention discloses a cache replacement method and device based on energy consumption characteristics of an MLC STR-RAM, and belongs to the technical field of computer storage, the MLC STR-RAM isused as a system main memory, the method comprises the following steps: when cache replacement occurs in a final-stage cache, respectively calculating N indexes of each cache block in the final-stagecache according to N preset cache replacement algorithms, respectively recording the indexes as a first index, a second index,..., and an Nth index of the corresponding cache block, respectively estimating write-back energy consumption generated by refreshing the data in each cache block back to the main memory, and taking the estimated write-back energy consumption as an (N + 1) th index of the corresponding cache block; comprehensively judging the N + 1 indexes of each cache block to select the eliminated cache block as a target cache block; wherein N is an integer greater than or equal to 1; in the N cache replacement algorithms, each cache replacement algorithm selects an eliminated cache block according to a single index, and the indexes of different cache replacement algorithms are different. According to the method, the write-back energy consumption of the MLC STT-RAM main memory can be effectively reduced.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and more specifically relates to a cache replacement method and device based on the energy consumption characteristics of MLC STT-RAM. Background technique [0002] With the rapid development of large-scale memory computing, DRAM (Dynamic Random-Access Memory) is the most widely used type of main memory, because of its small storage density, limited scalability, and huge power consumption caused by repeated refreshes. The disadvantage is that it can no longer meet the requirements of some real-time systems and high-performance systems for equipment area, performance and energy consumption. And energy consumption has always been a problem that cannot be ignored, and mainstream chip manufacturers have also introduced low-energy chip technologies. [0003] MLC STT-RAM (Multi-Level CellSpin Transfer Torque RAM, multi-level cell spin transfer torque magnetic random access memory) has become ...

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Problems solved by technology

[0004]The original cache replacement algorithm designed for DRAM as the main memory is not suitable for the main memory based on MLC STT-RAM. This is because the main memory based on DRAM In the cache, the data evicted according to the cache replacement strategy has fixed memory energy consumption when it is refreshed from the LLC to the main memory. Therefore, it is not necessary to consider the memory write energy consumption problem when designing the cache replacement strategy. The main source is the refresh of data, and MLC STT-RAM has asymmetric write energy consumption characteristics and high write energy consumption caused by two-step conversion, which makes it possible to apply the previous cache replacement strategy designed for DRAM to MLCSTT-RAM based When the main memory is used, it often brings serious write energy consumption problems

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