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Chip io pin verification system and method

A verification system and verification method technology, applied in the field of chip IO pin verification system, can solve the problem of low verification coverage of chip IO pins, and achieve the effect of improving efficiency

Active Publication Date: 2022-06-21
XIAMEN UNISOC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is to provide a chip IO pin verification system and method in order to overcome the low coverage defect of chip IO pin verification in the prior art

Method used

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  • Chip io pin verification system and method
  • Chip io pin verification system and method

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Experimental program
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Embodiment 1

[0044] This embodiment provides a chip IO pin verification system. refer to figure 1 , the chip IO pin verification system includes a host 1 and an auxiliary device 2 . The host 1 is connected to the chip under test 3 and the auxiliary device 2 in communication respectively. The host 1 configures the chip under test 3 to output a preset level signal on the configuration pin according to the preset test configuration; the configuration pin is the pin of the chip under test 3 other than the current pin to be tested, and the configuration pin is the same as the current pin to be tested. The test pins have a preset pairing relationship. In an optional embodiment, the host 1 is implemented by a PC (personal computer).

[0045] The auxiliary device 2 includes a number of auxiliary pins, the number of auxiliary pins is the same as that of the IO pins of the tested chip 3, and each auxiliary pin is electrically connected to an IO pin correspondingly. like figure 1 As shown, the f...

Embodiment 2

[0073] This embodiment provides a chip IO pin verification method. The chip IO pin verification method can be implemented by using the chip IO pin verification system of the first embodiment.

[0074] refer to image 3 , the chip IO pin verification method includes the following steps:

[0075] Step S1, the chip under test outputs a preset level signal on the configuration pin according to the preset test configuration. The configuration pins are pins of the chip under test other than the current pins to be tested, and the configuration pins and the current pins to be tested have a preset pairing relationship.

[0076] Step S2, according to the preset test configuration, the auxiliary device outputs the level signal on the configuration auxiliary pin on the object output pin PO1.

[0077] Step S3, the host reads the object output pin PO1, and configures the object input pin PI1 according to the level of the object output pin PO1.

[0078] Step S4, the auxiliary device outp...

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Abstract

The invention discloses a chip IO pin verification system and method, wherein the chip IO pin verification system includes a host and auxiliary equipment; the auxiliary equipment includes several auxiliary pins, and each auxiliary pin is electrically connected to an IO pin respectively ;The auxiliary device will configure the level signal on the auxiliary pin to output on the object output pin; the host reads the object output pin, and configures the object input pin according to the level of the object output pin; the auxiliary device outputs the object input pin The level signal on the pin is output on the auxiliary target pin; the chip under test responds to the level signal of the current pin under test according to the preset test configuration to generate result data, and save the result data to the test result file; the host reads Test the result file to determine whether the corresponding IO pin is normal. The invention does not need to manually switch the connection between the test equipment and the pins of the chip under test, which obviously improves the efficiency of test verification.

Description

technical field [0001] The invention belongs to the technical field of chip IO pin verification, and in particular relates to a chip IO pin verification system and method. Background technique [0002] In the process of chip design, the later the problem is found, the higher the wasted cost, especially after TO (tape-out), serious problems may need to be re-taped, resulting in high expenses and serious delays in the project. The chip contains many IO (input and output) pin-type interfaces, and completing the verification quickly and with a high coverage rate is conducive to the timely detection of defects in the chip and the improvement of chip quality. [0003] At present, the chip IO pin verification mainly includes the following schemes: [0004] Option 1: Manually randomly select some pins to configure registers directly, and the verification content is very limited. [0005] Option 2: Semi-automation: Generate some configuration items through tools and verify with the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/331G06F30/398
CPCG06F30/331G06F30/398
Inventor 赖太平
Owner XIAMEN UNISOC TECH CO LTD
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