Verification system, verification method and verification apparatus across multiple verification domains

Abstract

Disclosed are a verification system, a verification method and a verification apparatus across multiple verification domains, and a non-volatile computer readable storage medium across a plurality ofverification domains. The verification method across the multiple verification domains comprises the steps of obtaining test excitation across the multiple verification domains for verifying a to-be-verified object, wherein the test excitation across the multiple verification domains comprises a verification domain identifier for indicating at least one verification domain for executing the test excitation; analyzing the test excitation, and creating a verification transaction related to the to-be-verified object; and analyzing and executing verification transactions in a verification domainscorresponding to verification domain identifiers based on the verification domain identifiers.

Description

technical field [0001] Embodiments of the present disclosure relate to an authentication system, an authentication method, an authentication device, and a non-volatile computer-readable storage medium spanning multiple authentication domains. Background technique [0002] With the improvement of semiconductor manufacturing technology, SOC (System on Chip, system-on-chip) (that is, application-specific integrated circuit chip) and multi-core design solutions have been widely used instead of traditional integrated circuit chips. All these chip design solutions need to be functionally verified before use to ensure their reliability during use. As the scale of chip design continues to expand, the difficulty of verification, verification levels, types and numbers of verification domains are all in a state of sharp increase. In particular, there is less or almost no sharing between software verification and hardware verification of chip design, so test stimuli (test cases) for ve...

AI Technical Summary

Problems solved by technology

In particular, there is less or almost no sharing between software verification and hardware verification of chip design, so test stimuli (test cases) for verifying the same function need to be written in different languages ​​according to different verification levels or verification domains. The functional design of the chip design brings inconvenience

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