Method for aging trench gate VDMOS device and aging equipment

Abstract

The embodiment of the invention relates to a method for aging a trench gate VDMOS device and aging equipment. The method comprises the following steps: enabling a control circuit to output a first control signal, and controlling a controllable voltage source to apply a positive voltage to a drain electrode of a to-be-aged VDMOS device till the positive voltage reaches a breakdown voltage of the to-be-aged VDMOS device; within the set aging time, enabling the control circuit to acquire a first real-time monitoring signal of the drain-source current of the to-be-aged VDMOS device, acquiring a second real-time monitoring signal of the device surface temperature of the to-be-aged VDMOS device, and outputting a second control signal according to the first real-time monitoring signal and the second real-time monitoring signal; enabling the controllable voltage source to adjust the output voltage according to the second control signal to enable the drain-source current of the to-be-aged VDMOSdevice to be within a first preset range and the surface temperature of the device to be within a second preset range; and after timing is finished, cooling the to-be-aged VDMOS device, and taking out the to-be-aged VDMOS device from the aging equipment to obtain the aged trench gate VDMOS device.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a aging method and aging equipment for trench gate VDMOS devices. Background technique [0002] Before power devices are put into mass production and during the mass production process, in order to ensure that the life of the devices under working conditions can meet our requirements, an accelerated life simulation aging assessment of high temperature and high pressure will be arranged. At present, the reliability aging of vertical conductive double-diffused structure field effect transistors (VDMOS) includes high temperature drain-source voltage reverse bias (High temperature reverse bias, HTRB) and high temperature gate-source voltage reverse bias (High temperature gate bias, HTGB), where HTGB It is to carry out the aging assessment on the gate oxide between the gate and the source, because its voltage is low, generally not exceeding 20V. The HTRB assessment is g...

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Problems solved by technology

[0003] The split-gate trench VDMOS device almost relies on the entire trench to withstand the entire breakdown voltage, so the oxide layer at the bottom of the trench, especially the oxide layer at the bottom, bears a very large voltage field strength, so the quality of the oxide layer is very important for the reliability of the device. However, in the current conventional HTRB assessment, since the applied drain-source voltage is far lower than the breakdown voltage of the device, it is impossible to generate enough holes to inject into the oxide layer during the assessment, so it cannot be effectively and quickly Investigate split gate trench VDMOS devices, that is to say, the current assessment method has certain limitations for trench gate VDMOS, especially for the latest trench gate structure-separated gate trench VDMOS devices.

In addition, the aging process of the current HTRB assessment also lacks automatic monitoring and control

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