Multi-core processor

Abstract

The invention discloses a multi-core processor. The multi-core processor comprises a first processor, at least one first-class slave device connected with the first processor through an upper bus, a second processor and at least one second-class slave device connected with the second processor through a lower bus, wherein the upper bus is connected with the lower bus through a bilateral slave device; the first processor is a main device on the upper bus; and the second processor is the only main equipment on the lower bus. Because only one master device exists in the lower bus, the situation that a plurality of master devices compete for the bus, and a bus arbitration mechanism needs to be arranged in the bus to arbitrate the request for accessing the bus occupied by the plurality of master devices is avoided, and therefore the real-time performance in the lower bus environment is improved.

Description

technical field [0001] The present application relates to processor technology, in particular to a multi-core processor. Background technique [0002] A multi-core processor refers to the integration of two or more complete computing engines (cores) in one processor. At this time, the processor can support multiple processors on the system bus, and the bus controller provides all bus control signals and command signal. [0003] Multi-core processors can be classified into a symmetrical multi-processing (SMP) structure and an asymmetrical processing structure. A common symmetric processing structure can be as figure 1 As shown, a processor, direct memory access (direct memory access, DMA), flash memory (flash), static memory (static RAM, SRAM) and other external devices (referred to as peripherals) can be connected to the bus; the bus can be A simple bus can also be a matrix bus; the processor can also be connected to an interrupt controller. Among them, the processor and...

AI Technical Summary

Problems solved by technology

Therefore, most of the current multi-core processors sacrifice hard real-time performance for the sake of efficiency and full utilization of bandwidth.

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