Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Metallization lamination layer, manufacturing method thereof and electronic device comprising metallization lamination layer

A metallization and stacking technology, applied in the direction of circuits, electrical components, electrical solid devices, etc., can solve the problems of increasing manufacturing costs, integrated circuit short circuit or open circuit faults, etc., to increase integration density, reduce line width or CD and The effect of spacing

Pending Publication Date: 2020-04-10
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
View PDF13 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, it is difficult to align the metal lines with the vias, which can lead to short or open failures in the integrated circuit (IC) and thus increase the manufacturing cost of the IC

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Metallization lamination layer, manufacturing method thereof and electronic device comprising metallization lamination layer
  • Metallization lamination layer, manufacturing method thereof and electronic device comprising metallization lamination layer
  • Metallization lamination layer, manufacturing method thereof and electronic device comprising metallization lamination layer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0013] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a metallization lamination layer, a manufacturing method thereof and electronic equipment comprising the metallization lamination layer. According to an embodiment, a metallization stack may include at least one interconnect layer and at least one via layer alternately disposed on a substrate. At least one pair of adjacent interconnect line layer and via layer in the metallization stack includes interconnect lines in the interconnect line layer and via holes in the via layer, wherein the interconnect line layer is closer to the substrate than the via layer. At least a portion of the interconnect line is integral with a via hole on the at least a portion of the interconnect line.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and more particularly, to metallization stacks, methods of making the same, and electronic devices including such metallization stacks. Background technique [0002] With the continuous miniaturization of semiconductor devices, it is becoming more and more difficult to manufacture high-density interconnect structures because of the need for extremely thin metal lines (meaning small grain size, excessive barrier layer thickness and thus high resistance) and Extremely small line spacing (meaning misalignment, difficulty filling contact holes). In addition, it is difficult to align the metal lines with the vias, which can lead to short or open failures in the integrated circuit (IC), and thus increase the manufacturing cost of the IC. Contents of the invention [0003] In view of this, an object of the present disclosure is at least in part to provide a metallization stack, a method of manu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/522H01L23/528H01L23/538
CPCH01L23/5283H01L23/5226H01L23/5386H01L21/76885H01L21/7682H01L23/528H01L23/53242H01L21/76816H01L21/823475H01L21/76837H01L23/53257
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com