Host end mapping method and device of SSD array, computer device and storage medium

A technology of computer equipment and mapping methods, applied in the direction of input/output process of computing, memory system, data processing, etc., can solve the problems of uneven wear, no concurrent write performance, no concurrent write performance, etc., to ensure concurrency, Meet the demand and ensure the effect of wear leveling

Pending Publication Date: 2019-12-24
SHENZHEN YILIAN INFORMATION SYST CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing SSD array host-side mapping strategy adopts a simple fragmented static mapping strategy: For example, taking an array composed of two SSDs as an example, host LBA0 / 2 / 4 / 6... are mapped to Disk 1's LBA 0 / 1 / 2 / 3…; host LBA 1 / 3 / 5 / 7… are mapped to Disk 2’s LBA 0 / 1 / 2 / 3… in turn; since the host’s LBA writing may be random, for example, the host centrally writes the host LBA 0 / 2 / 4, then only disk 1 is providing write at this time. On the one hand, disk 1 wears out too quickly, and on the other hand, the writing performance is not concurrent. Only one disk is working, resulting in uneven wear, and Write performance cannot be concurrent; therefore, requirements cannot be met

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  • Host end mapping method and device of SSD array, computer device and storage medium
  • Host end mapping method and device of SSD array, computer device and storage medium
  • Host end mapping method and device of SSD array, computer device and storage medium

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Embodiment Construction

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0035] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude one or Presence or addition of multiple other features, integers, steps, operations, elements, components and / or collections thereof.

[0036] It should also be understood that the terminology used ...

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Abstract

The invention relates to a host end mapping method and device of an SSD array, a computer device and a storage medium. The method comprises the following steps of S1, creating a mapping table; S2, acquiring a request from a host; S3, performing read / write processing on the request of the host according to the mapping table to obtain a processing result; and S4, feeding back a processing result tothe host. By creating the mapping table, the logic spaces of different SSDs can be sequentially allocated for storing the write-in data of the host, so that any write-in data of the host can be written into each SSD of the SSD array in a balanced manner, the wear balance is guaranteed, the concurrency of the write-in performance is guaranteed, and the requirements can be better met.

Description

technical field [0001] The present invention relates to the technical field of solid-state hard disks, and more specifically refers to a host-side mapping method, device, computer equipment and storage media of SSD arrays. Background technique [0002] SSD (Solid State Drive) has been widely used in various occasions. At present, in the PC market, it has gradually replaced the traditional HDD, providing users with a better experience in terms of reliability and performance. As the main storage medium of SSD, NAND ( Memory) has been updated; with the evolution of the process, the reliability of the particles is facing greater challenges. Within a given number of erasing and writing of NAND, as the PE (erasing and writing times) increases, the probability of error will also increase. Increase. [0003] In order to meet the correctness requirements of the data, in addition to traditionally increasing the ECC error correction capability and using the NAND built-in ReadRetry (re...

Claims

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Application Information

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IPC IPC(8): G06F3/06G06F12/1027
CPCG06F3/061G06F3/0629G06F3/0688G06F12/1027
Inventor 王猛徐伟华
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD
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