Data acquisition system-oriented blockage dredging bypass type router design method

Abstract

The invention discloses a data acquisition system-oriented blockage dredging bypass type router design method, which comprises the following steps of: micro-architecture design: determining bypass input and output ports of a router according to a data transmission path and a data transmission mode of the router; designing a working time sequence: planning a data transmission time sequence according to the function requirement of blockage dredging; arbitration design: designing an arbitration mechanism of the router according to function requirements, and determining a data transmission path. According to the situation that some routers are blocked in the data transmission process and other routers on the same layer are in an idle state in a data collection system, a novel router is designed, and a solution is provided for dredging blockage and improving the data transmission rate. The bypass type router designed from three aspects of micro-architecture design, working time sequence design and arbitration design can transmit data packets to an upper-layer router and can dredge the data packets to a same-layer router, thereby effectively preventing the occurrence of a blocking condition.

Description

technical field [0001] The invention relates to a router of an on-chip network, in particular to a design method for a blocking, dredging and bypassing router oriented to a data acquisition system. Background technique [0002] In the macroscopic computer Internet, routers play a pivotal role. A router is a bridge of a computer network, through which it can not only connect different networks, but also select the path of data transmission and block illegal access. As the core equipment of IP network, the technology of router has become the key technology of current information industry, and its equipment itself plays an increasingly important role in data communication. [0003] Network on Chip (NoC) technology is the application of computer network technology in chips such as microprocessors. The interconnect structure of the network on chip is composed of three parts: network interface, router and link. Among them, the network interface is used to convert the data forma...

AI Technical Summary

Problems solved by technology

[0007] The on-chip network composed of two entry routers can complete the task of data collection, but the network composed of routers has two characteristics, one is the aggregation effect, and the other is that the top-level router will limit the throughput of the entire network

The aggregation effect will cause the upper router to have a large amount of data, and in some cases, even cause the entire network to be blocked

At the same time, the data transmission rate of the topmost router will limit the throughput of the entire network

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