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Semiconductor device and forming method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as poor performance of interconnect structures, and achieve the effects of improving performance, simplifying steps, and avoiding positional deviation

Active Publication Date: 2019-10-18
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, existing interconnect structures perform poorly

Method used

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  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof
  • Semiconductor device and forming method thereof

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Experimental program
Comparison scheme
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Embodiment Construction

[0027] As mentioned in the background, semiconductor devices formed by the prior art have poor performance.

[0028] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor device forming process.

[0029] refer to figure 1 , to provide the layer 100 to be etched.

[0030] continue to refer to figure 1 , etch part of the layer 100 to be etched, and form discrete first trenches 111 and second trenches 112 in the layer 100 to be etched, and the extension directions of the first trenches 111 and the second trenches 112 are parallel to the first The alignment direction between the trenches 111 and the second trenches 112 .

[0031] refer to figure 2 , a through hole 120 is formed in the layer to be etched 100 between the first trench 111 and the second trench 112 .

[0032] Subsequent steps further include: forming a first conductive layer in the first trench 111 ; forming a second conductive layer in the second trench 112 ; and forming a conduc...

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Abstract

The invention discloses a semiconductor device and a forming method thereof. The method comprises the steps of forming a first mask material layer on a to-be-etched layer, wherein the first mask material layer comprises a barrier area; forming discrete first mask groove and second mask groove in the first mask material layer, wherein the extension directions of the first mask groove and the secondmask groove are parallel to the arrangement direction between the first mask groove and the second mask groove; and the first mask groove and the second mask groove are located at two sides of the barrier area separately; exposing a side wall in the barrier area to form a barrier layer; etching one part of barrier area of the first mask material layer by taking the barrier layer as a mask and forming a first mask through hole in the barrier area of the first mask material layer; and etching the to-be-etched layer by taking the barrier layer and the first mask material layer as masks and correspondingly forming a first groove, a second groove and a through hole in the first mask groove, the second mask groove and the to-be-etched layer at the bottom of the first mask through hole. According to the method, the performance of the semiconductor device is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same. Background technique [0002] Interconnect structures are often required to be formed in the semiconductor integrated circuit process. The interconnect structure is used to electrically connect the upper and lower material layers. The interconnect structure includes a conductive layer and a conductive plug, the conductive layer is located in the trench, and the conductive plug is located in the through hole. [0003] The positions of the through holes and trenches are usually designed according to the needs of the design. Some vias need to be located between adjacent trenches, and vias and trenches are separated from each other. [0004] However, existing interconnect structures have poor performance. SUMMARY OF THE INVENTION [0005] The problem solved by the present invention is to provide a semic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528
CPCH01L21/76816H01L23/5283H01L2221/101H01L21/76897H01L21/486H01L21/76843H01L21/7688
Inventor 张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP
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