Port connection method and system for improving verification environment reusability and medium

Abstract

The invention discloses a port connection method and system for improving reusability of a verification environment, and a medium, and the method comprises the steps: defining a port connection macrofor connecting a DUT port signal with the verification environment, determining the connection direction of a signal according to the hierarchy of the verification environment, and driving the DUT port signal through a verification module when the hierarchy of the verification environment is a module level; when the level of the verification environment is a subsystem level, sampling a port signalof the DUT with a verification component; and connecting the signals which can be reused by the module-level verification and the subsystem-level verification by using the port connection macros. Theconnection direction of the signal is determined according to the hierarchy of the verification environment, the reuse problem can be effectively solved, the verification workload is saved, errors caused by manual reconnection of the signal are avoided, and the verification efficiency is improved.

Description

technical field [0001] The invention relates to chip verification, in particular to a port connection method, system and medium for improving the reusability of the verification environment. Background technique [0002] Verification is an indispensable process in the chip product development process to prove whether the design function is realized and implemented correctly. In order to better complete the verification, the verification personnel need to often build an appropriate and efficient verification environment around the design. With the increasing scale and complexity of chips and the rapid development of chip verification technology, there are various ways to build a verification environment. At present, the reusable hierarchical verification platform is commonly used in the industry, such as figure 1 As shown, from low to high, it is divided into signal layer, command layer, function layer, scene layer and test layer. The verification environment includes gener...

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Problems solved by technology

[0012] The number of DUT port signals is often hundreds or thousands. Connecting so many signals requires a huge workload. The signal connection work of different levels of verification environments must be done again, which will inevitably cause waste, and is prone to errors, reducing verification efficiency.

[0013] If the module-level verification (BT, BlockTest) environment can be reused by subsystem-level verification / integration verification (IT, IntegrationTest), efficiency can be improved, but due to figure 2 For the reason shown in , reuse needs to change the driving direction of the port, and the port connection of DUT and verification environment needs to be developed separately due to different signal directions at different verification levels, so it cannot be reused

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