Synchronous counter

Abstract

The invention discloses a synchronous counter. The synchronous counter comprises an input end COUNTER ENABLE, an input end, CLOCK, an output end CARRY, an output end CARRY_B, a state output end Q0, astate output end Q1, a state output end Q2 and a state output end Q3, a trigger DFF1, a trigger DFF2, a trigger DFF3, a trigger DFF4, a trigger DFF5, a two-input NAND gate ND1, a two-input NOR gate NR1, a two-input NAND gate ND2, a two-input NOR gate NR2, a two-input NAND gate ND3, a two-input NOR gate NR3 and a NOR gate INV1, wherein the input ends and the output ends of the trigger DFF1, the trigger DFF2 and the trigger DFF4 respectively comprise an input end EN1, an input end T1, an output end Q1 and an output end QN1; the input ends and the output ends of the trigger DFF3 and the trigger DFF5 respectively comprise an input end ENB, an input end T2, an output end Q2 and an output end QN2; the input end COUNTER ENABLE is connected with the input end EN1 of the trigger DFF1, the input endof the two-input NAND gate ND1 and the input end EN1 of the trigger DFF2.

Description

technical field [0001] The present invention relates to the technical field of circuit elements, in particular to a synchronous counter. Background technique [0002] As is well known, as a circuit element, a synchronous counter uses a plurality of flip-flops that respond to a clock of a fixed period to count up or down. In addition, synchronous counting is also used as an indispensable part in general integrated circuits, especially in semiconductor memories that perform data access operations by inputting address signals. [0003] figure 2 The flip-flop units used in the test are all T-type flip-flops: if the control terminal EN is high, the state of the flip-flop is flipped once when the clock terminal T finds the rising edge of the clock; if the control terminal EN is low, the flip-flop maintains the original state constant. figure 2 (a) is a serial carry, figure 2 (b) is parallel carry. figure 2 As shown in (a), the carry signal Q0 needs to be delayed by three AND ...

AI Technical Summary

Problems solved by technology

In addition, the load of each flip-flop is inconsistent, and the synchronization performance of each state in the synchronization counter will also be affected

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