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Multi-fault tolerant deterministic path routing method for ultra-large-scale network-on-chip

A network-on-chip, ultra-large-scale technology, applied in data exchange networks, digital transmission systems, electrical components, etc., can solve the problems of sacrifice, can not ensure that NoC has enough available node design requirements, etc., to achieve the effect of small single-hop delay

Active Publication Date: 2021-09-03
TONGJI UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the algorithm sacrifices all original fault-free nodes contained in the unsafe region
Therefore, this algorithm is not suitable for NoCs with numerous faults, since it can hardly ensure that the NoC has enough available nodes to meet the design requirements

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Embodiment Construction

[0057] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is carried out on the premise of the technical solution of the present invention, and detailed implementation and specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

[0058] 1. Relevant definitions and related indicators

[0059] 1. Related definitions

[0060] Network On Chip (Network On Chip, NoC): Network On Chip is a new communication method between IP cores in a system on chip. NoC is an important part of multi-core technology, which brings a new way of thinking to on-chip communication, which is obviously superior to traditional bus-based systems. The NoC-based system is more suitable for the local synchronous global asynchronous clock mechanism in the future multi-core complex SoC design. NoCs address the scalability issues of system-on-c...

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Abstract

The invention relates to a deterministic path routing method for ultra-large-scale on-chip network to tolerate multiple faults. The method maintains a routing table on each switch of the on-chip network, and each switch performs online routing based on the routing table, and the routing table is offline. Generation, the generation process includes: calculating the maximum strongly connected component of the network on chip based on the Tarjan algorithm, deleting faulty nodes and faulty links, using the breadth-first traversal strategy to traverse the remaining nodes and links of the network on chip, and generating a routing table. Compared with the prior art, the present invention not only tolerates the impact of multiple failures, but also maximizes the available nodes in the reconstructed NoC, and outperforms existing solutions in terms of average delay, throughput, and energy consumption.

Description

technical field [0001] The invention belongs to the technical field of network-on-chip architecture design and routing, and relates to a routing method for a super-large-scale network-on-chip, in particular to a deterministic path routing method for a super-large-scale network-on-chip that tolerates multiple faults. Background technique [0002] With powerful parallel communication capabilities, large-scale network-on-chip has become the most promising structure in supercomputers. The wafer-level NoC (Network On Chip, network on chip) can move a large number of parallel communications between chips to the inside of the chip, which reduces transmission delays and thus significantly improves computing performance. At the same time, since a single chip is used as a small supercomputer, this structure can make supercomputers more energy-efficient. Therefore, the development of wafer-level NoC has become an effective measure to further improve the performance of supercomputers. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/703H04L12/741H04L12/751H04L12/24H04L45/28H04L45/02H04L45/74
CPCH04L45/28H04L45/54H04L45/02H04L41/0816H04L41/0659
Inventor 张颖陈中胜季鹏飞江建慧
Owner TONGJI UNIV
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