Multiple-bit comparator with reliable output timing and reduced hazards

Abstract

A multi-bit comparator that compares individual bits of a first multi-bit signal with corresponding bits of a second multi-bit signal. The output control circuit in the multi-bit comparator detects whether the second signal is active or inactive based on the change in the second signal, and maintains the output signal at a fixed logic level when the second signal is inactive. When the second signal is active, the output signal is controlled according to the combined result of the respective bit comparisons. The individual bit comparison results are preferably combined using wired OR logic.

Description

field of invention [0001] The present invention relates to a method of comparing multi-bit input signals and multi-bit comparators for use in content addressable memories such as cache memories. technical background [0002] A multi-bit comparator accepts a pair of multi-bit input signals and produces an output signal that indicates whether each bit of the two input signals is the same. In a cache memory, one input signal gives the address of the requested data word, and another input signal gives the address of the superspeed data word. The output signal indicates that if the two addresses are the same, the result is called a cache hit, or if the output signal is different, the result is called a cache miss. [0003] The classic circuit structure of a multi-bit comparator that will be described below consists of an XOR gate that compares the bits of the two output signals, and a NOR gate that combines the outputs of the XOR gates to produce the final output signal. This s...

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Problems solved by technology

This hazard also creates timing design difficulties, as it must ensure that the output signal is sampled at a point where failure is avoided as much as possible

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