Display device, gate driving circuit, shift register and control method thereof

Abstract

The invention discloses a display device, a gate driving circuit, a shift register and a control method thereof. The shift register comprises an input module, a first output module, a second output module and a first reset module, wherein the input module is used for setting a pull-up node as valid working potential under the control of a signal input terminal; the first output module is used forwriting the voltage of a clock signal terminal into a cascade signal output terminal under the control of the pull-up node; the second output module is used for writing the voltage of a first power terminal into a gate signal output terminal under the control of the pull-up node; and the first reset module is used for setting the gate signal output terminal and the pull-up node as invalid workingpotential under the control of the first reset signal terminal. The shift register disclosed by the embodiment of the invention separates the cascade signal output terminal and the gate signal outputterminal, thereby connecting a clock signal to a smaller transistor, reducing the inter-electrode capacitance, and thus reducing the power consumption of the gate driving circuit.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a shift register, a gate drive circuit, a display device and a control method for the shift register. Background technique [0002] With the popularity of electronic products such as mobile phones and notebooks, consumers and terminal manufacturers pay more and more attention to the power consumption performance of electronic products. As an important component of an electronic product, the power consumption saving of a display device such as a liquid crystal display (Liquid Crystal Display, LCD) is particularly important. Wherein, the array substrate row driving circuit (Gate Driver on Array, GOA) is used as the driving circuit of the LCD display, and more than 80% of its power consumption is generated by a clock signal with a relatively high frequency. [0003] In the GOA circuit of the related art, the clock signal is usually connected to the transistor with the larg...

AI Technical Summary

Problems solved by technology

However, the problem with related technologies is that there is a large overlapping area between the gate and the drain of the transistor, which will form a large capacitance of pF or even nF level. All capacitors will generate repeated charging and discharging, resulting in a large current, which will result in a large power loss

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