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Parallelization optimization method for SM3 cryptographic hash algorithm

A technology of hash algorithm and optimization method, which is applied in the field of security password application, can solve the problems of not being able to make full use of non-vector processor computing resources, and cannot improve the operation speed of a single SM3 cryptographic algorithm, and achieve the effect of eliminating assignment operations and simplifying assignments

Active Publication Date: 2019-03-29
PEKING UNIV
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Problems solved by technology

[0004] The current mainstream Intel / AMD X86 processors and ARM processors can both support the calculation of non-vector instruction sets and vector instruction sets. On the computing platforms of ARM / NEON instruction sets and X86 / AVX2 instruction sets, conventional parallel algorithms , often execute multiple SM3 algorithms in parallel through vector registers, but such algorithms cannot make full use of the computing resources of non-vector processors during execution, and cannot improve the operation speed of a single SM3 cryptographic algorithm

Method used

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  • Parallelization optimization method for SM3 cryptographic hash algorithm
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Embodiment 1

[0818] Embodiment 1: Realization of ARM / NEON instruction set

[0819] The ARM processor is currently the mainstream processor used in smart mobile devices such as mobile phones. Among them, the most widely deployed Cortex-A series ARM processor architecture includes not only the ARM general-purpose instruction set (ARMv7 instruction set), but also the NEON SIMD instruction set. The NEON instruction set contains 16 128-bit SIMD registers, which can perform parallel calculations of 4-way 32-bit words. Therefore, the vector calculation in the 4-way parallel algorithm of the SM3 compression function in this paper can be implemented with NEON instructions, and other instructions can be implemented with conventional ARM Realization of general instructions, which can be written in high-level language and realized by compiling.

[0820] The NEON instructions used are given below. These instructions are given in the form of pseudo functions (Intrinsics), where int32x4_t is a 128-bit NE...

Embodiment 2

[0825] Embodiment 2: Implementation of X86 / AVX2 instruction set

[0826] Non-vector code can be written in a high-level language and implemented through compilation, and vector algorithms are implemented using AVX2 instructions

[0827] Use the command _m256i c = _mm256_xor_si256(_m256i a, _m256i b)

[0828] c←a<<

[0829] Vector shift left _mm256_sllv_epi32(_m256i a, _m256i count)

[0830] Vector shift right _mm256_srlv_epi32(_m256i a, _m256i count)

[0831] vector or _mm256_or_si256(_m256i a, _m256i b)

[0832] The overall execution statement is as follows:

[0833] _mm256i c=mm256_or_si256(_mm256_sllv_epi32(a,k),_mm256_srlv_epi32(a,32-k))

[0834] c←a+b: use the command _m256i c=_mm256_xor_si256(_m256ia, _m256i b)

[0835] c←b:_m256ic=_mm256_stream_load_si256(_m256i const*mem_addr_of_b)

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Abstract

The invention discloses a parallelization optimization method for an SM3 cryptographic hash algorithm. The SM3 cryptographic hash algorithm comprises an SM3 message extension function and an SM3 message compression function; a multi-channel parallel algorithm is adopted, cyclic operation in the SM3 cryptographic hash algorithm is unfolded, and multiple rounds of iteration are combined, so that theoperation required by the SM3 cryptographic hash algorithm is simplified; a potential parallel operation vector in the extended SM3 cryptographic hash algorithm is realized so as to realize internalparallelization of the SM3 cryptographic hash function; the parallelization optimization method can run on a computing platform supporting simultaneous execution of a vector instruction and a non-vector instruction. According to the method in the invention, the internal parallelization of the SM3 cryptographic hash function is realized, and the operation speed is further increased; and when the method is applied to the computing platform capable of executing the vector instruction and the non-vector instruction at the same time, the computing speed is higher.

Description

technical field [0001] The invention belongs to the technical field of security cipher application, and relates to a parallel optimization algorithm of SM3 password hash function, and the realization of the parallel algorithm on SIMD (Single Instruction, Multiple Data) instruction set. It specifically relates to the 4-way parallel algorithm and 8-way parallel algorithm of SM3, and the specific embodiments of these two parallel algorithms on the ARM / NEON instruction set and the AVX2 instruction set. Background technique [0002] Cryptographic hash (Hash) function is a kind of basic cryptographic algorithm with a wide range of uses. In addition to calculating the hash value of data, it is also a basic component of many cryptographic schemes and security protocols such as digital signatures and message authentication codes. Commonly used cryptographic hash functions include the SHA-1 algorithm released by the National Institute of Standards and Technology (NIST), the SHA-2 seri...

Claims

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Application Information

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IPC IPC(8): H04L9/06H04L9/08H04L9/32
CPCH04L9/0643H04L9/0863H04L9/3236
Inventor 关志陈霄王珂李青山陈钟
Owner PEKING UNIV
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