PDN alternating current noise analysis method for a three-dimensional integrated circuit

Abstract

The invention discloses a PDN alternating current noise analysis method of a three-dimensional integrated circuit, which is used for analyzing the magnitude of PDN alternating current noise of the three-dimensional integrated circuit. The method comprises the following implementation steps: (1) constructing three physical models; (2) obtaining respective parasitic parameter values of the three physical models; (3) calculating parasitic parameter values; (4) obtaining simulated parasitic parameter values; (5) constructing an equivalent circuit model of the power distribution network PDN; (6) setting a power distribution network PDN alternating current noise simulation environment; And (7) obtaining the maximum alternating current noise of the power distribution network PDN of the three-dimensional integrated circuit. The method can quickly and accurately analyze and obtain the magnitude of the alternating current noise of the PDN of the three-dimensional integrated circuit, and can be used for providing a basis for design analysis of the integrity of the power supply in the power distribution network of the high-speed three-dimensional integrated circuit and evaluation of the packaging reliability.

Description

technical field [0001] The invention belongs to the field of electronic technology, and further relates to a power distribution network PDN (Power Distribution Network) AC noise analysis method of a three-dimensional integrated circuit in the field of high-speed circuit power distribution technology. The measurement and analysis results of the PDN AC noise in the power distribution network of the high-speed three-dimensional integrated circuit provided by the invention can be used to provide a basis for the design analysis of the power supply integrity in the power distribution network of the high-speed three-dimensional integrated circuit and the evaluation of the packaging reliability. Background technique [0002] With the continuous improvement of chip integration, the number of transistors increases exponentially, and the problem of chip power integrity becomes increasingly prominent. Most of the three-dimensional packaging technologies use TSV (Through Silicon Vias) to...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the parasitic parameters of the power line / ground line, through-silicon vias TSV and VIA through-holes in the power distribution network PDN need to be calculated through EM modeling and simulation, which directly leads to slow analysis of AC noise ; In addition, when the chip load is equivalent to an alternating current source, the current waveform is a triangular pulse, and the continuous change of the current will cause the measured AC noise to be inaccurate

The disadvantage of this method is that it only considers the influence of the parasitic parameters of the TSV, and ignores the influence of the parasitic parameters of the power line / ground line and the VIA through hole in the power distribution network PDN changing with frequency, which leads to the simulation AC noise results are inaccurate

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