3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The 3D memory device includes: a semiconductor substrate; a gate stack structure located on the semiconductor substrate, including a plurality of alternately stacked gate conductors and a plurality of interlayer insulating layers; and a plurality of channel columns passing through the gate stack structure , and is electrically connected to the semiconductor substrate; the 3D memory device also includes a conductive column, which runs through the gate stack structure, is electrically connected to the semiconductor substrate, and is distributed between a plurality of channel columns, and each conductive column is used to pass through the semiconductor substrate. The bottom supplies power to the surrounding channel posts.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared...

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Problems solved by technology

However, in a 3D memory device, the conductive channel only supplies power to the channel pillars on both sides of it, so it is necessary to form a plurality of gate line spacers first, and then fill the gate line spacers to form a conductive channel after forming the channel columns. The process is complicated, and the conductive channel needs to occupy a large amount of space in the 3D memory device. In addition, because the conductive channel needs to fill the entire gate line spacer, not only is it difficult to control the warpage of the wafer, but also more consumables and higher costs

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