A Design Method for Embedded Core Test Package Scan Chain

Abstract

The present invention proposes a kind of embedded core test packaging scan chain design method, including step (1): algorithm initialization; step (2): de-initialization step (3): if the end condition is not satisfied, continue, otherwise go to step (12 ); Step (4): Estimate the objective function max(s i ,s o ) value; step (5): adjust food sources and enemies; step (6): adjust individual separation S, individual direction A, individual cohesion C, individual food F, position D and weight of individual enemies w; Step (7): Evaluate S, A, C, F, and D; Step (8): Adjust the neighborhood radius; Step (9): Adjust the location vector; Step (10): Validate according to the bounds of the variables and Modify the new position, if the value of the new position is less than 1, set its value to 1, if it is greater than N, then set its value to N; step (11): go to step (3); step (12): Output the result.

Description

technical field [0001] The invention relates to the field of a system on chip (System-on-Chip, SoC), in particular to a design method for an embedded core test package scan chain. Background technique [0002] Today, advanced silicon chip manufacturing makes it possible to integrate more transistors, which allows hundreds of embedded cores with various structures including random access memory (RAM), read-only memory (ROM) on a single chip , digital signal processor (DSP), combinational logic block (CLB) and central processing unit (CPU), etc. This pattern becomes essential in SoC design as the reuse of pre-designed and pre-verified embedded cores significantly reduces the overall design cycle and cost. However, as the density of embedded cores increases, defects and failures in SoCs become more severe. Therefore, the verification and testing of embedded cores is of great significance to a successful SoC design. Test development is also recommended to be core-based to avo...

AI Technical Summary

Problems solved by technology

However, as the density of embedded cores increases, defects and failures in SoC become more serious

Images