A preparation method of a shielded gate power device

Abstract

An object of the present invention is to provide a preparation method of a shielded gate power device. A double-layer different resistivity epitaxy is adopted, the lower layer is low resistance epitaxy, which has smaller on-state resistance than the homogeneous high resistance epitaxial layer under the same withstand voltage to reduce the static power loss of the device, the gate oxide longitudinally extends to the drain, and the transverse electric field distribution of the upper layer high resistance layer is optimized by a Resurf technology, so as to improve the reverse withstand voltage ofthe device. As the shield gate is PN-doped polysilicon, the capacitance between the shield gate and the drain can be reduced so as to reduce the switch power loss of the shielded gate power MOSFET.

Description

technical field [0001] The invention relates to a method for preparing a power device, in particular to a method for preparing a shielded grid power device. Background technique [0002] Since the invention of power MOS technology, there have been many important developments and advancements in the technology. In recent years, new device structures and new manufacturing processes of power MOS technology have emerged continuously to achieve two basic goals: maximum power handling capability and minimum power loss. [0003] The existing structure mostly adopts single-layer uniform resistivity epitaxy, because of its large on-state resistance and large static power loss; the shielded gate is uniform N-type doped polysilicon, and the capacitance between the shielded gate and the drain is relatively large. The switching power loss of the power MOSFET is relatively large. Contents of the invention [0004] In order to solve the above problems, the object of the present inventi...

AI Technical Summary

Problems solved by technology

[0003] The existing structure mostly adopts single-layer uniform resistivity epitaxy, because of its large on-state resistance and large static power loss; the shielded gate is uniform N-type doped polysilicon, and the capacitance between the shielded gate and the drain is relatively large. The switching power loss of the power MOSFET is large

Images