A single-wire serial half-duplex communication method with wide clock tolerance

Abstract

The invention relates to a single-line serial half-duplex communication method with wide clock tolerance. The master sends a serial data frame to a slave during communication, and the slave receives and returns a serial data frame. When the data line is idle, the data line is in a high level, when the serial data frame is transmitted, the starting bit is a low level of the time length D, each databit comprises two parts of a continuous clock synchronization unit and a data representation unit, the clock synchronization unit is a high level of the time length A, and the data 0 and 1 in the data representation unit are low levels of the time length B and C, respectively. A clock synchronization unit and a data representation unit detect a start bit, detect a data bit, and detect a data representation unit after detecting a clock synchronization unit when the data bit is detected. This method can effectively avoid the communication error caused by the accumulated error in the continuoustransmission of multiple data bits in the communication process, and has a complete serial data frame initiation and verification mechanism.

Description

technical field [0001] The invention relates to a wide clock tolerance single-line serial half-duplex communication method, which belongs to the technical field of communication control. Background technique [0002] For some household appliances, such as water heaters, air conditioners, etc., the control part is generally installed in a remote location far from the user, while the operation and display part is installed in a location that is easy for the user to touch. Since the operation display part and the control part are far away, In order to reduce the complexity of installation and wiring, the two generally use communication to exchange data. [0003] The split controllers of household appliances usually use UART (Universal Asynchronous Transceiver) non-return-to-zero coding asynchronous half-duplex or full-duplex serial communication between different boards. Due to the characteristics of non-return-to-zero coding, the clock error of the communication chip will Acc...

AI Technical Summary

Problems solved by technology

With the advancement of technology and technology, many microcontroller chips can achieve a clock error of 1%-5% in the entire operating voltage and temperature range. However, the clock error of most chips is still at the level of 2% or above, which cannot To meet the requirement that the total clock error of both communication parties is within 3.7%, which limits the design options and design methods of microcontroller chips to a large extent, and in most cases, models that support external resonators or external clocks have to be used to meet the requirements. Communication clock accuracy requirements increase product complexity

In the prior art, in order to reduce the influence of accumulated errors in the process of receiving data, various solutions have appeared, but their effects are not satisfactory, and some methods cannot effectively solve the problem of synchronization and verification of data frame transmission and reception; some The method cannot distinguish the first pulse as the start signal from the interference pulse, and because the bus level is in an uncertain state when the bus is idle, it increases the difficulty of design, and at the same time in the specific pulse interference sequence and the critical state of the communication clock tolerance erroneous data will inevitably be received under

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