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Pre-compression method and system of integrated circuit layout planning

An integrated circuit and pre-compression technology, applied in electrical digital data processing, instruments, computing and other directions, can solve the problems of increasing production costs, reducing work efficiency, consuming more time, etc., to achieve the effect of improving utilization and reducing production costs

Active Publication Date: 2018-11-30
FOSHAN SHUNDE SUN YAT SEN UNIV RES INST +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current method adopts the random initialization method, randomly arranges the sequence composed of module numbers, and obtains the sequence pair and However, this method has obvious disadvantages, such as Figure 8 As shown, the corresponding circuit modules of the random initialization sequence are very scattered, and most of the modules are located outside the preset layout box, so it takes more time to fill these blank areas in the later optimization algorithm, which reduces the workload. Efficiency, there is a wide range of blank areas, which will also increase the area of ​​the circuit layout and increase the production cost

Method used

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  • Pre-compression method and system of integrated circuit layout planning
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  • Pre-compression method and system of integrated circuit layout planning

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] Such as figure 1 As shown, a pre-compression method for integrated circuit layout planning, including the following steps:

[0055] A1. Obtain the preset array information and the sequence pair information of the interrelationship among multiple modules including the integrated circuit, as well as the parameter information of each module. The parameter information is length information, width information, area information and type information of the module.

[0056] A2. After laying out each module in the preset layout frame in sequence combined with the sequence pair information and array information, determine whether there is an occlusion module based on the parameter information and the preset judgment method. If there is, use the first method to update the array information; otherwise , using the second method to update the array information. The array information includes parameter information of the left border of the layout box, parameter information of the l...

specific Embodiment 1

[0073] Combine below Figure 2 to Figure 14 The above method is explained in detail.

[0074] Assuming that the integrated circuit contains six modules, the serial numbers of the six modules are abcdef, and their dimensions are shown in Table 1.

[0075] Table 1

[0076]

module a

module b

module c

module

module e

module f

width

8

6

3

5

7

3

high

4

3

5

5

6

7

[0077] Also assume that the sequence pairs for this circuit layout are as follows.

[0078]

[0079] An array en is set, which stores: the left border of the circuit layout frame, represented by the letter l; the lower border of the circuit layout frame, represented by the letter s; and the module number.

[0080] First place l and s respectively in the positive sequence The head end and the end end, get

[0081] The first module in the reverse sequence is module d, and the sequence pair is According to the sequence pair pr...

Embodiment 2

[0099] A pre-compression system for layout planning of integrated circuits, comprising:

[0100] memory for storing at least one program;

[0101] The processor is configured to load the at least one program to execute any one of the pre-compression methods for integrated circuit layout planning described above.

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Abstract

The invention discloses a pre-compression method and system of integrated circuit layout planning. The method includes following steps: acquiring array information, sequence pair information containing a mutual relation among multiple modules of an integrated circuit and parameter information of each module; sequentially combining the sequence pair information with the array information to lay outeach module in a layout frame, combining the parameter information with a preset judging mode to judge whether there is a blocking module or not, and if yes, adopting a first mode to update the arrayinformation; if not, adopting a second mode to update the array information; judging whether all modules are laid out or not according to the sequence pair information, and if yes, completing pre-compression; if not, continuing executing the previous step. By judging whether there is the blocking module or not and combining the sequence pair information with the array information to lay out the next module after the array information is updated if yes, working efficiency and utilization rate of layout area are improved, production cost is lowered, and the pre-compression method and system canbe widely applied in the field of physical design of the integrated circuit.

Description

technical field [0001] The invention relates to the field of physical design of integrated circuits, in particular to a pre-compression method and system for layout planning of integrated circuits. Background technique [0002] At present, the design of large-scale integrated circuits must rely on computer-aided design tools, so the efficiency of the tools has a great impact on the design time of the circuit. At present, the physical design of integrated circuits mainly includes two parts: layout representation and optimization algorithm. The computer uses the layout representation to convert the actual circuit into a code form that it can handle, and then uses a specific optimization algorithm to optimize each module in the circuit. Layout is performed to obtain a circuit module layout with smaller area and better other specific indicators. [0003] At present, the sequence pair notation is mainly used to represent the distribution of modules (circuit layout) in an integra...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 谭洪舟梁耀淦谢舜道陈荣军朱雄泳曾衍瀚路崇
Owner FOSHAN SHUNDE SUN YAT SEN UNIV RES INST
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