Delay calibration parameter determination method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a delay calibration parameter determination method and device, electronic equipment and a storage medium. The method comprises the steps that according to analternative delay value set corresponding to to-be-calibrated data ports, a Monte Carlo tree of delay values is constructed, wherein nodes on each layer of the Monte Carlo tree correspond to alternative delay values of the same to-be-calibrated data port; according to delay values of iterative value paths in the Monte Carlo tree, delay values needed for all the to-be-calibrated data ports to output standard test signals are adjusted, and a target value path is obtained; and according to all the nodes included in the target value path, delay values corresponding to all the to-be-calibrated dataports are determined. Through the technical scheme in the embodiment, the technical effect of determining delay calibration parameters automatically, efficiently, rapidly and accurately is achieved,no manpower cost investment is needed, an existing delay calibration parameter determination mode is optimized, and the determination efficiency of the delay calibration parameters is improved.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of data processing, and in particular, to a method, device, electronic device, and storage medium for determining delay calibration parameters. Background technique [0002] At present, with the continuous development of various high-precision and highly integrated equipment, how to realize the delay calibration between each chip in the equipment and the delay calibration between each data port in the same chip has become a very important research nowadays. topic. [0003] For example, in the design and manufacture of instrumentation technology, it is often necessary to realize the reception of radio frequency signals, which requires the use of ADC (Analog-to-Digital Converter, analog-to-digital converter) to convert the analog signal into a digital signal, and then enter the FPGA (Field- Programmable Gate Array, Field Programmable Gate Array) to process or analyze digital signals....

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Problems solved by technology

[0004] In the process of implementing the present invention, the inventor found that the prior art has the following defects: when the number of data ports requiring delay adjustment is large, and there are many alternative delay values ​​corresponding to the data ports, each data port The number of delay adjustment schemes is too large. It is very difficult, time-consuming and labor-intensive to find a suitable value only manually. It requires a lot of attempts, and it is difficult to achieve the desired result.

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