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Real-time super-resolution method and system based on FPGA

A technology of super-resolution and interpolation method, applied in the field of image processing, which can solve the problems of difficult practical application, high computational cost, insufficient output frame rate, etc.

Active Publication Date: 2018-11-06
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Model-based methods aim to recover high-resolution scenes based on observation models and priors (regularization). Most of the existing techniques assume known blur kernels and noise levels, but in practice the blur kernels and noise levels can be arbitrary. , assuming that it is known to cause difficulties in practical applications, the effect is not good
Neural network-based super-resolution often has a high computational cost, and often faces the problem of insufficient output frame rate when processing video in real time

Method used

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  • Real-time super-resolution method and system based on FPGA
  • Real-time super-resolution method and system based on FPGA
  • Real-time super-resolution method and system based on FPGA

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Embodiment 1

[0098]Preferred embodiment one: consists of three main parts:

[0099] · Scheduling module: Calculate the TV value of each block according to the equation mentioned above. Blocks whose TV values ​​are greater than a predetermined threshold are then assigned to the neural network, while other values ​​are assigned to the interpolation module.

[0100] Pipelined neural network: FSRCNN-s is a pipelined structure implemented in the pipeline stage. The number of multipliers per stage is also configured to achieve a balanced throughput of the stage.

[0101] · Interpolation module: Simple and fast interpolation module, which handles modules whose TV value is lower than the threshold. Bilinear algorithm can improve image quality with lower operation cost and better performance. Finally, the data blocks output from the network or interpolation components are combined to generate the final output high-resolution image.

[0102] In a TV-based mask, the vertical and horizontal gradie...

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PUM

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Abstract

The invention discloses a real-time super-resolution method and system based on an FPGA, and relates to the technical field of image processing. The method comprises the steps of splitting each frameof image in a medium with a relatively low resolution into sub-images for performing super-resolution processing; allocating a processing module according to an eigenvalue of the current frame of thesub-image; if the eigenvalue is relatively high, performing calculation by a neural network module; and if the eigenvalue is relatively low, performing calculation by an interpolation module. An output buffer outputs the high-resolution sub-images obtained by calculation and recombines the sub-images into a high-resolution image, so that a user can see the real-time ultra-high-definition image.

Description

technical field [0001] The invention relates to the technical field of image processing, in particular to a field-programmable gate array (FPGA)-based real-time super-resolution method and system. Background technique [0002] Ultra High Definition (UHD) technology is dramatically changing the media industry, with high-resolution displays now dominating the market. However, the supply of ultra-high-definition media resources is limited, and access is difficult due to insufficient network bandwidth, and the actual user experience is still mediocre. Therefore, it is of great significance to efficiently upscale 1920×1080 traditional high-definition (2K FHD) video to 4K UHD resolution (3940×2160). The technique of estimating fine-grained resolution images / videos from low-resolution inputs is often referred to as super-resolution, and this fundamental problem is very attractive in the fields of image processing and computer vision. [0003] Field-programmable gate array (FPGA)-...

Claims

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Application Information

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IPC IPC(8): G06T3/40G06T5/10G06T7/11G06N3/08
CPCG06N3/08G06T3/4053G06T5/10G06T7/11G06T2207/20132
Inventor 罗国杰何卓论黄瀚贤柏园超贾惠柱姜明
Owner PEKING UNIV
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