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FPGA implementation method of fiber channel 64-bit parallel scrambling and descrambling

An implementation method, 64-bit technology, applied in instruments, computers, calculations, etc., can solve the problems of difficult FPGA implementation and high speed, and achieve high-speed results

Active Publication Date: 2020-09-18
电信科学技术第五研究所有限公司
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Problems solved by technology

[0004] However, in Fiber channel communication, the rate is usually high, sometimes even up to 8Gbit / s, and it is difficult to implement FPGA with 32 channels of parallelism, so a higher parallelism FPGA implementation solution is required

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  • FPGA implementation method of fiber channel 64-bit parallel scrambling and descrambling
  • FPGA implementation method of fiber channel 64-bit parallel scrambling and descrambling
  • FPGA implementation method of fiber channel 64-bit parallel scrambling and descrambling

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Embodiment Construction

[0024] The FPGA implementation method of the Fiber channel 64-bit parallel scrambling and descrambling device described in the present invention includes a scrambling implementation method and a descrambling implementation method.

[0025] The scrambling implementation method is as follows figure 1 Shown, is to use an XOR tree and a delay unit ( figure 1 In D) realize 64 parallel scramblings, the output of the XOR tree is the output after scrambling; the input data of the delay unit is the output data of the XOR tree, and the output data of the XOR tree is delayed After time processing, it is used as the output data of the delay unit.

[0026] The input data of the XOR tree is the 64-bit parallel data that needs to be scrambled and the 64-bit data output by the delay unit. The 64-bit data obtained after the input data is calculated is used as the output data of the XOR tree. The calculation formula is:

[0027] Formula 1: Bits 1-39 of the output data are:

[0028] Formu...

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Abstract

The invention provides an FPGA implementation method for a Fibre channel 64-bit parallel scrambling / descrambling device. The method comprises a scrambling implementation method and a descrambling implementation method. According to the scrambling implementation method, one XOR tree and one delay unit are utilized to realize 64-channel parallel scrambling. According to the descrambling implementation method, one XOR tree and one delay unit are utilized to realize 64-channel parallel descrambling. A high-parallelism FPGA scrambling implementation scheme is provided, wherein one XOR tree and onedelay unit are adopted to realize 64-channel parallel scrambling; and one XOR tree and one delay unit are adopted to realize 64-channel parallel descrambling. The method can better meet the requirement for a high rate in Fibre channel communication.

Description

technical field [0001] The invention belongs to the technical field of parallel scrambling and descrambling devices, in particular to an FPGA implementation method of a Fiber channel 64-bit parallel scrambling and descrambling device. Background technique [0002] In the Fiber channel standard, when using the 8B / 10B transmission mode, in order to reduce the probability of long character repetition, the sending end needs to use frame scrambling, and the receiving end needs to use frame descrambling. Frame scrambling is done by XORing the pseudo-random sequence generated by a linear feedback shift register with the transmitted data. The polynomial corresponding to the linear feedback shift register is G(x)=x 58 +x 39 +1, the initial value of 58 bits is the lower 58 bits of the hexadecimal number 029438798327338h. Frame descrambling can be done by XORing the input signal with its linearly shifted signal. [0003] In the Fiber channel standard, a 32-bit parallel input scrambl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
CPCG06F15/17318
Inventor 舒勇朱力翟大海王昌庆
Owner 电信科学技术第五研究所有限公司
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