An Asynchronous Clock Generation Circuit for 2-bit-per-cycle SAR ADC

Abstract

The invention discloses an asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC, including a comparator conversion completion flag signal generation unit, a gating signal generation unit, an intermediate comparator judgment completion flag signal generation unit, and a comparator Asynchronous clock generating unit, wherein, the output signal of the comparator conversion completion flag signal generating unit and the conversion clock Conv are used as the input signal of the gating signal generating unit; the output signal Q2 / of the intermediate comparator of the 2-bit-per-cycle SAR ADC QB2 is the input signal of the intermediate comparator judgment completion flag signal generation unit; the output signal of the gating signal generation unit and the intermediate comparator judgment completion flag signal generation unit is used as the input signal of the comparator asynchronous clock generation unit; the comparator asynchronous clock generation unit The output signal is used as the asynchronous clock for the first to third comparators. In the case of realizing high-speed data conversion, this kind of circuit avoids the use of an external clock that is multiple times higher than the sampling rate, and at the same time avoids the problem of easy occurrence of synchronous metastability.

Description

technical field [0001] The invention belongs to the technical field of analog-digital hybrid integrated circuits, and in particular relates to an asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC. Background technique [0002] The asynchronous successive approximation analog-to-digital converter (SAR ADC) is widely used because of its low power consumption, high digitization, and no need for multiplier clocks. However, the traditional asynchronous SAR ADC is essentially a serial structure, that is, the working principle of 1-bit-per-cycle known to the public, which greatly limits its application in high-speed applications. In recent years, the research on speed-up of SAR ADC is in full swing. [0003] Among them, in 2015, Hyeok-Ki Hong of the Korean Academy of Science and Technology proposed a 2-bit-per-cycle synchronous 7-bit SAR ADC in the Journal of Solid-State Circuits (JOURNAL OF SOLID-STATE CIRCUITS), which requires 5 times the sampling freque...

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Problems solved by technology

[0003] Among them, in 2015, Hyeok-Ki Hong of the Korean Academy of Science and Technology proposed a 2-bit-per-cycle synchronous 7-bit SAR ADC in the Journal of Solid-State Circuits (JOURNAL OF SOLID-STATE CIRCUITS), which requires 5 times the sampling frequency The external clock, and in order to correct the problems caused by the metastable state, digital correction technology is used, which may require the use of digital back-end technology, which increases the system complexity and design difficulty

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