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FPGA operation circuit and solution method of Spearman rank correlation coefficients

A technology for computing circuits and computing results, applied in electrical digital data processing, computing, digital data processing components, etc.

Active Publication Date: 2018-09-21
GUANGDONG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In the prior art, on the one hand, the CPU is often used to calculate and solve the SR, but because the CPU mainly adopts a serial calculation method, it is limited by the limitations of serial operations, resulting in a time-consuming calculation and solution of the SR by the CPU; On the one hand, there is also the use of FPGA to design mathematical operation circuits to calculate and solve SR, but it requires two signals X i , Y i Find the rank P i and Q i , two sorting circuits are required, not only there is a problem of long time consumption, but also the circuit structure is relatively complicated

Method used

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  • FPGA operation circuit and solution method of Spearman rank correlation coefficients
  • FPGA operation circuit and solution method of Spearman rank correlation coefficients
  • FPGA operation circuit and solution method of Spearman rank correlation coefficients

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Embodiment 1

[0058] The generalized relative coefficient explains the internal relationship among PPMCC, KT and SR. make Represents n pairs of independent and identically distributed data pairs generated by the binary continuous distribution parent; the data pair sequence according to Arranged in ascending order, a new set of data pair sequences can be obtained where X 1 n is an ordinal statistic about X, and the corresponding Y [i] call it X (i) accompaniment; assuming X j in sequence The kth position in , then define the number k as X j rank of , denoted as P j ; Similarly put Y j The rank of is defined as Q j . The generalized correlation coefficient is defined as follows:

[0059]

[0060] when a ij =P j -P i and b ij =Q j -Q i The Spearman rank-order correlation coefficient can be derived γ s , which is the Spearman rank correlation coefficient derived from the generalized correlation coefficient using the original method. After research, the inventor found...

Embodiment 2

[0100] see figure 2 , is a schematic flowchart of a method for solving the Spearman rank-order correlation coefficient provided in Embodiment 2 of the present invention. The method is performed by the FPGA computing circuit provided by the embodiment of the present invention, and the steps are as follows:

[0101] S11. Signal X i Send it to the row and column storage block to get X 1 …X i …X n and x 1 …X j …X n , to complete the first-level cache;

[0102] S12, the X obtained in step S11 1 …X i …X n and x 1 …X j …X n into the comparator array to complete the n 2 comparison operation to get a ij =sign(x j -x i ), and sent to the pipeline to complete the secondary cache;

[0103] S13. Signal Y i Send it to the sorting circuit to get the rank Q 1 …Q n , the process is done in parallel n 2 second sorting operation;

[0104] S14. Rank Q 1 …Q n Send it to the row and column storage block to get Q 1 …Q i …Q n and Q 1 …Q j …Q n , to complete the first-l...

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Abstract

The embodiment of the invention discloses an FPGA operation circuit and a solution method of Spearman rank correlation coefficients. The circuit comprises a comparator array, a subtracter array, an array multiply accumulator, a multiplier, a square root extractor, a divider, a sorting circuit, a row and column storage block, an assembly line, a control unit and a register. The FPGA operation circuit and the solution method of Spearman rank correlation coefficients have the advantages that partial definition equations of the Spearman rank correlation coefficients derived by generalized correlation coefficients are improved, thereby being capable of simplifying an FPGA operation hardware circuit designed based on the generalized correlation coefficients, accelerating the arithmetic speed, and achieving the purpose of solving SR quickly in real time.

Description

technical field [0001] The embodiment of the present invention relates to the technical field of data processing, and in particular to an FPGA operation circuit and a method for solving the Spearman rank correlation coefficient. Background technique [0002] Correlation analysis originated in the pioneering period of statistics in the 1900s, and is still a research hotspot in the field of statistical signal processing. The so-called correlation is an index that characterizes the strength of the statistical relationship between two random variables or two signals. If one random variable increases (decreases) as the other random variable increases (decreases), the two random variables satisfy a positive correlation; conversely, if one random variable increases (decreases) as the other random variable Large (decrease) and decrease (increase), then the two random variables satisfy a negative correlation. In biomedicine, the correlation analysis of multi-channel signals (brain ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/575
CPCG06F7/575
Inventor 陈昌润徐维超章云
Owner GUANGDONG UNIV OF TECH
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