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A configuration method of network chip calendar in mixed rate mode

A configuration method and network chip technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve problems such as relatively complex, difficult to configure multi-rate mixed calendar, scheduler cannot meet bandwidth requirements, etc., to improve development Efficiency and complexity reduction effects

Active Publication Date: 2021-10-15
SUZHOU CENTEC COMM CO LTD
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  • Claims
  • Application Information

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Problems solved by technology

For example, according to Table 1 above, assuming that there are two 100G queues in the scheduler, Σ=(1 / 1.87)+(1 / 1.87)=1.06, which does not meet the expectations, in this case the scheduler cannot meet the bandwidth of the two 100G queues need
[0013] When the total bandwidth of all members in the scheduler is close to the physical limit of the scheduler, that is, the total bandwidth Σ approaches 1, and the discrete data interval is used to satisfy the T that is accurate to decimal places. avg is more complicated
It is very difficult to configure a multi-rate mixed calendar without the support of the algorithm

Method used

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  • A configuration method of network chip calendar in mixed rate mode
  • A configuration method of network chip calendar in mixed rate mode

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Embodiment Construction

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.

[0035] A method for configuring a network chip calendar in a mixed rate mode disclosed by the present invention can automatically produce calendar configuration through a calendar (time adaptation) convergence algorithm without manual calculation. Especially when multiple rates are mixed and the total bandwidth of all members in the scheduler is close to the physical limit of the scheduler, it can greatly reduce the complexity of system configuration and improve the efficiency of system development.

[0036] Such as figure 2 As shown, a method for configuring the network chip calendar in the mixed rate mode disclosed by the embodiment of the present invention includes:

[0037] Step 1, calculate the total bandwidth Σ of all queues in the scheduler, if the value of the total bandwidt...

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Abstract

The present invention discloses a configuration method of a network chip calendar in a mixed rate mode, which includes setting an interval counter and a list of effective flag bits for each queue in the scheduler, and traversing all the queues when each round of convergence starts to calculate, if all If the interval counter value corresponding to the queue index is greater than the index itself, then select the queue whose effective flag bit is 1 and has the smallest interval counter and remove it from the effective flag bit list; otherwise, select the queue with the smallest interval counter from the effective flag bit list queue, and remove it from the list of valid flags; after that, all interval counters are decremented by 1, and the selected queue resets the interval counter. The invention can automatically produce calendar configuration without manual calculation, especially when multi-rate mixing and the total bandwidth of all members in the scheduler are close to the physical limit of the scheduler, it can greatly reduce the complexity of system configuration and improve the efficiency of system development.

Description

technical field [0001] The invention relates to a multi-rate mixed Calendar configuration technology, in particular to a configuration method of a network chip calendar in a mixed-rate mode. Background technique [0002] Calendar is a time-adapted scheduling method, which can ensure that all members waiting to be scheduled are evenly scheduled out according to the preset ratio. To implement calendar scheduling, a two-dimensional data structure needs to be designed, and the value of each address in the data structure corresponds to the scheduled queue ID. Set a start address and end address at the same time, and use a counter to accumulate. When the counter is incremented to the end address, the value of the counter returns to the start address. Generally, we set the starting address to 0, such as figure 1 shown. [0003] figure 1 , the values ​​in the data structure are 1 / 3 / 5 / 1 / 3 / 1 (don’t care about the calendar data value beyond the end address), the start address is 0...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/873H04L12/24H04L47/52
CPCH04L41/0889H04L47/52
Inventor 徐子轩唐飞
Owner SUZHOU CENTEC COMM CO LTD
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