esd device structure

An ESD device, P-LDMOS technology, applied in the direction of semiconductor devices, electrical solid state devices, electrical components, etc., can solve problems such as large latchup risk

Active Publication Date: 2021-06-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the maintenance voltage Vh of the pure SCR structure after snapback generally does not exceed 10V, and there is a greater risk of latchup in the application of high-voltage ports.

Method used

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Examples

Experimental program
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Embodiment Construction

[0043] The ESD device structure of the present invention includes: a first LDMOS, a second LDMOS and a parasitic SCR;

[0044] The first PLDMOS and the second LDMOS are P-LDMOS with the same structure and layout sharing a high-voltage P-well (HVPW), and the high-voltage P-well (HVPW) between the drain of the first P-LDMOS and the drain of the second P-LDMOS The parasitic SCR formed by the N+ region is arranged in the middle, and the first P-LDMOS and the second P-LDMOS form a left-right asymmetric structure centering on the N+ region of the parasitic SCR. The width (A1+B1) of the field oxygen region between the gate and drain of the first LDMOS is greater than the width (A2+B2) of the field oxygen region between the gate and drain of the second LDMOS, so that the structure can be reduced Turn on the voltage.

[0045] Such as image 3 As shown, a specific embodiment of the ESD of the present invention includes: P-type substrate Psub, the first high-voltage N well HVNW1, the s...

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Abstract

The invention discloses an ESD device structure, including: a first P-LDMOS, a second P-LDMOS and a parasitic SCR; the first P-LDMOS and the second P-LDMOS share a high-voltage P-well (HVPW). A parasitic SCR formed by an N+ region is set in a high-voltage P well (HVPW) between a P-LDMOS drain and a second P-LDMOS drain. The first P-LDMOS and the second P-LDMOS have the same structure, and the parasitic The N+ region of the SCR forms a left-right asymmetric structure at the center. The invention can improve the ESD capability after the device is turned on, and can also increase the maintenance voltage and current of the device, and reduce the latch-up risk of the ESD device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an ESD device structure. Background technique [0002] Static electricity is an objective natural phenomenon, which can be produced in many ways, such as contact, friction, induction between electrical appliances, etc. Static electricity is characterized by long-term accumulation, high voltage, low power, small current and short action time. Static electricity poses serious hazards in at least two areas. Friction electrification and human body static electricity are two major hazards in the electronics industry, which often cause unstable operation or even damage of electronic and electrical products. ESD is a discipline formed since the middle of the 20th century to study the generation, harm and protection of static electricity. It is customary in the world to refer to the equipment used for electrostatic protection as ESD. [0003] Conventional high-voltage ESD devices general...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0266
Inventor 邓樟鹏苏庆韦敏侠
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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