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An efficient clock tree physical location optimization method for integrated circuit semi-custom backend design

A technology of physical location and integrated circuits, applied in electrical digital data processing, computer-aided design, calculation, etc., can solve the problem of no unified and efficient clock tree design physical placement optimization method, shorten the chip design cycle and improve design quality , reduce the effect of ineffective work

Active Publication Date: 2021-08-03
嘉兴倚韦电子科技有限公司
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  • Application Information

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Problems solved by technology

[0003] At present, there is no uniform and efficient method for optimizing the physical placement of clock tree design in the industry

Method used

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  • An efficient clock tree physical location optimization method for integrated circuit semi-custom backend design
  • An efficient clock tree physical location optimization method for integrated circuit semi-custom backend design
  • An efficient clock tree physical location optimization method for integrated circuit semi-custom backend design

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Embodiment Construction

[0027] The present invention discloses a method for optimizing the physical location of an efficient clock tree in integrated circuit semi-customized back-end design. The specific implementation of the present invention will be further described below in combination with preferred embodiments.

[0028] see attached Figure 1 to Figure 6 , image 3 The specific flow of the method for optimizing the physical location of the high-efficiency clock tree in integrated circuit semi-custom back-end design is shown.

[0029] see attached image 3 and Figure 4 and Figure 5 , the integrated circuit semi-customized back-end design efficient clock tree physical location optimization method includes the following steps:

[0030] Step S1: The back-end design tool checks one by one according to the chip shape and the electrical parameters of the components and judges whether each physical position of the clock tree is reasonable. If it is reasonable, check the next physical position of ...

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Abstract

The invention discloses a method for optimizing the physical position of an efficient clock tree in integrated circuit semi-customized back-end design. Step S1: The back-end design tool checks one by one according to the chip shape and the electrical parameters of the components and judges whether each physical position of the clock tree is reasonable. If it is reasonable, check the next physical position of the clock tree, otherwise mark the physical position and execute step S2 . Step S2: scanning the chip area corresponding to the marked physical position in step S1, and marking the physical effective area in the chip area. The method for optimizing the physical location of an efficient clock tree for integrated circuit semi-customized back-end design disclosed by the present invention improves the design quality of clock tree design, helps improve chip design work efficiency, reduces invalid work and design iterations, and ultimately shortens the chip design cycle. .

Description

technical field [0001] The invention belongs to the technical field of design automation EDA in the integrated circuit design industry, and in particular relates to a method for optimizing the physical position of an efficient clock tree for semi-customized back-end design of integrated circuits. Background technique [0002] Clock tree design plays an important role in chip design. In the clock tree design, it is necessary to optimize the design multiple times according to the initial design quality, and the quality of the clock tree design is very important. [0003] At present, there is no unified and efficient method for optimizing the physical placement of clock tree design in the industry. Improving the quality of clock tree design through an efficient clock tree physical location optimization method, thereby improving the work efficiency of the entire project, is a technical problem that needs to be urgently solved in the current status of semi-customized back-end de...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/398G06F30/396G06F30/392
CPCG06F30/392G06F30/398G06F2119/18
Inventor 徐靖
Owner 嘉兴倚韦电子科技有限公司
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