Processing method and device for queue operation

Abstract

The invention discloses a processing method for a queue operation. The method includes the following steps: obtaining a queue number of a queue to which message information to be processed belongs; querying storage location information and address information of a queue descriptor corresponding to the queue number in a mapping table; obtaining the queue descriptor according to the storage locationinformation and the address information of the queue descriptor, moving the queue descriptor to a register, and updating the storage location information and the address information of the queue descriptor corresponding to the queue number in the mapping table; and performing a queue operation on the message information to be processed according to the queue descriptor, and updating the queue descriptor according to the queue descriptor and the updated storage location information and address information of the queue descriptor after the queue operation is performed. The invention also discloses a processing device for the queue operation at the same time.

Description

technical field [0001] The present invention relates to the technical field of the Internet, in particular to a processing method and device in queue operation. Background technique [0002] In a network device, such as a network processor (Network Processor, NP), a switching access (Fabric Access Processor, FAP), a switch, a bridge, or a traffic management chip, all integrate a queue management function, and packets are processed according to queues. With the growth of business, the number of queues that network devices need to support increases exponentially, and has reached 512K or even more than 1M queues. The difficulty of queuing management for a large number of high-density queues increases accordingly. Queues and queue identifiers That is, the storage of the queue descriptor (Queue Descriptor, QD) needs to occupy a large amount of storage capacity. On the premise of ensuring the performance, reducing the cost of the chip must be considered. [0003] In the prior art...

AI Technical Summary

Problems solved by technology

However, there are three problems in this method. First, the read and write bandwidth of CAM cannot be expanded arbitrarily. When writing to CAM frequently, the queue number maintained by CAM changes frequently, which will inevitably affect the efficiency of CAM retrieval; second, The CAM with the same capacity occupies a larger area and consumes more power than the Cache. The CAM cannot support enough QD tags at the same time, so the number of QDs placed in the Cache will be affected by the CAM capacity; third, high-speed high-performance traffic management requires a large On-chip QD storage with large capacity and operating bandwidth, Cache cannot support large capacity and large read and write bandwidth at the same time

It can be seen that in the queue operation, this method requires frequent access to Cache and DRAM to obtain QD, which leads to low access efficiency of QD

[0005] Therefore, in order to solve the problem of low QD access efficiency in queue operations, it is urgent to find a processing method in queue operations

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