Field-effect transistor structure and fabrication method thereof

Abstract

The invention provides a field-effect transistor structure and a fabrication method thereof. The fabrication comprises the steps of providing a substrate, and depositing at least one layer of first material and at least one layer of second material on a surface of the substrate; defining an active region and a shallow groove isolation region; etching the active region to form a channel region, a source region and a drain region; corroding the first material layer or the second material layer in the channel region to obtain at least one nanowire channel; depositing a dielectric layer and a gridstructure layer on a surface of the nanowire channel; and fabricating a grid electrode, a source electrode and a drain electrode on surfaces of the grid structure layer, the active region and the drain region to complete fabrication of the field-effect transistor. By the scheme, the stacked Si or SiGe material layer forms the three-dimensional stacked annular grid nanowire channel, the cross section of the channel is expanded on the same planar region, the device performance is improved, the grid control capability is improved, the device stability is also improved, the carrier transmission capability is improved as well as the device size is reduced, the device performance is improved, the source-drain doping step is omitted, and the technology is simple in process.

Description

technical field [0001] The invention relates to the technical field of semiconductor device structure and its preparation, in particular to a field effect transistor structure and its preparation method. Background technique [0002] In recent years, with the continuous advancement of microelectronics technology, the feature size of devices has been reduced and the performance of devices has been continuously increased. Due to the reduction of device feature size, a series of short-channel effects such as leakage-induced barrier reduction have continuously strengthened the suppression effect on device performance, which seriously affects the reliability of the device and inhibits the improvement of device performance. For this reason, starting from the 22nm technology generation, the Fin Field-Effect Transistor (FinFET) structure has become the mainstream microelectronics manufacturing technology. The multi-gate structure of FinFET greatly improves the control ability of the...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a structure of a field effect transistor and a preparation method thereof, which are used to solve the problem that the carrier transport capability of the nanowire field effect transistor in the prior art is limited by nanometer The diameter of the line channel and the difficulty of source-drain ion implantation

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