Method and system for optimizing chip area and power consumption

Abstract

The invention provides a chip area and power consumption optimization method and system. The chip area and power consumption optimization method includes the following steps of analyzing the read-write frequency within a single clock cycle of a register; if the read-write frequency within the single clock cycle of the register is low, carrying out SRAM specification selection; substituting the register with an SRAM; carrying out data reading synchronization. The chip area and power consumption optimization method and system can effectively reduce the area and power consumption of a processor and meanwhile generate less influences on the performance, and therefore the overall performance power consumption ratio of the processor is improved.

Description

technical field [0001] The invention relates to the field of chip design and structure optimization, in particular to a chip area and power consumption optimization method and system. Background technique [0002] With the development of computer architecture, the domain-specific computer architecture has become the main development trend. When facing specific applications, the special-purpose structure uses the application characteristics to optimize the structure accordingly, so as to better exert the computing performance of the hardware. In the field of high-performance computing, data flow computing is an important branch of domain-specific computing structures, and data flow computing has shown good performance and applicability. [0003] At present, the data flow structure processor chip integrates a large number of storage units. These storage units store the instructions, data and control information that need to be executed in advance, which can avoid frequent memo...

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Problems solved by technology

[0005] However, in the current data flow structure processor and some heterogeneous computing acceleration processors, some storage adopts the register structure, such as the instruction storage module, but due to the limitation of the execution unit in these processors, it is impossible to execute a large number of instructions in one clock cycle. Instead, it can only execute a few instructions, and the instruction storage module stores hundreds of instructions, so it does not make full use of the characteristics of register independent reading, which is a waste of using registers and a waste of precious area resources of the chip. , since the area is proportional to the power consumption, it also causes waste of power consumption

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