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Layout wiring scheme tMesh of multi/many-core framework TriBA-CMPs

A technology of layout and routing and routing methods, which is applied in the field of layout and routing solutions of multi-core architecture TriBA-CMPs, can solve problems such as unfavorable process implementation, and achieve the effect of simple and easy layout and routing

Active Publication Date: 2017-12-29
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0033] The purpose of the invention is to solve the problem that adopting "Y" type layout and wiring in TriBA-CMPs is not conducive to process realization, and proposes a layout and wiring scheme tMesh of TriBA-CMPs with many / many-core architectures

Method used

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  • Layout wiring scheme tMesh of multi/many-core framework TriBA-CMPs
  • Layout wiring scheme tMesh of multi/many-core framework TriBA-CMPs
  • Layout wiring scheme tMesh of multi/many-core framework TriBA-CMPs

Examples

Experimental program
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Effect test

Embodiment 1

[0093] In tMesh's wiring-related claims, there are options of first horizontal and then vertical or first vertical and then horizontal, Figure 5 Both options are characterized with a 3-core (i.e., 1-layer) tMesh layout. In this figure, when the upper left and lower right coreTiles of TriBA-cNoC are interconnected, they can be wired horizontally and then vertically or vertically and then horizontally; the coreTile and L 2 When interconnecting, wiring can be done horizontally and then vertically or vertically and then horizontally.

Embodiment 2

[0095] Because TriBA-mNoC may have multiple input and output ports in the actual implementation, so its horizontal (vertical) connection may exist Image 6 Multiple connections are shown. In TriBA-mNoC wiring of layer f tMesh, upper left and lower right L in layer f-1 tMesh f Level Cache units are respectively connected with L in layer f tMesh f+1 When level Cache is connected, L f Level Cache unit has 2 f-2 cacheTile and L f+1 Level Cache is horizontally and vertically adjacent respectively, so they can be accessed through 2 f-2 The horizontal and vertical wiring are connected, and can also be connected through 2 f-2 Any one or more of the horizontal and vertical wirings are connected to each other; L in the lower left f-1 layer tMesh f Level Cache unit and L in layer f tMesh f+1 Level Cache connected, through the L f cacheTile and L in the upper right corner of the level Cache unit f+1 The cacheTile in the lower right corner of the level Cache unit is connected to r...

Embodiment 3

[0097] Such as Figure 7 As shown, tMesh can be applied after horizontal or vertical reflection and rotation at any angle to meet different application requirements.

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Abstract

The invention relates to a layout wiring scheme tMesh of a multi / many-core framework TriBA-CMPs, and belongs to the technical field of computer system structures, high-performance calculation and multi / many-core processor system structures. Based on a basic three-layer recursion expandable characteristic of the TriBA-CMPs, the layout wiring scheme tMesh is proposed: f layers of tMesh are realized by arranging (f-1) layers of 3 tMesh located in a top left region, a bottom left region and a bottom right region respectively, and an Lf+1 level Cache unit in a top right region; when the (f-1) layers of the 3 tMesh are mutually connected to realize wiring of the f layers of the tMesh, the top left region and the bottom left region, the bottom left region and the bottom right region and the top left region and the bottom right region are connected respectively through longitudinal, transverse, longitudinal and transverse or transverse and longitudinal wiring; and the Lf+1 level Cache unit is connected with 3 Lf level Cache units in the (f-1) layers of the 3 tMesh located in the top left region, the bottom right region and the bottom left region respectively through transverse, longitudinal, longitudinal and transverse or transverse and longitudinal wiring. Compared with conventional 2D-mesh-Tile, the layout wiring scheme not only has the advantages of concise layout wiring and easy realization of a final process, but also has a very good layered expandable characteristic.

Description

technical field [0001] The present invention relates to a layout and wiring scheme of multi / many-core architecture TriBA-CMPs, in particular to adopting the tMesh scheme to realize the layout and wiring of TriBA-CMPs, belonging to the technical field of computer architecture, high-performance computing, and multi- / many-core processor architecture . Background technique [0002] Multi-core processors have become the research and development direction of high-performance processor architecture, and the on-chip communication architecture has an extremely important impact on the performance of multi-core processors. At present, 2D mesh is widely used as the mainstream network-on-chip (hereinafter referred to as NoC) architecture, such as figure 1 The topology of the 2D mesh network shown is the simplest and most intuitive topology, and has the same intuitive, simple and efficient Tile layout and routing scheme (hereinafter referred to as 2D-mesh-Tile). [0003] Tile is the bas...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/18G06F30/392
Inventor 石峰魏增辉王一拙王小军陈旭
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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