FPGA chip, high-speed interface interconnection system and interconnection achieving method

Abstract

The invention relates to an FPGA chip, a high-speed interface interconnection system and an interconnection achieving method. The FPGA chip is characterized by comprising an FPGA chip body, the FPGA chip body comprises a high-speed interface and a training unit, the high-speed interface comprises a high-speed interface module, and the high-speed interface module is connected with a transmitting module and a receiving module; the training unit comprises a data selection module, and the data selection module is connected with a training module and a detection module; the data selection module is connected with a design module; the data selection module is connected with the high-speed interface module; the FPGA chip body and the high-speed interface of at least another one FPGA chip. An automatic interconnection mechanism of the high-speed interface is put forwards, the high-speed interface interconnection success rate is increased, artificial participation is reduced, the debugging process is accelerated, and therefore the FPGA prototype verification period and the chip development period are greatly shortened.

Description

technical field [0001] The invention belongs to the technical field of FPGA prototype verification of server interconnection chips, and particularly relates to an FPGA chip, a high-speed interface interconnection system and a method for realizing interconnection. Background technique [0002] With the increasing number and complexity of business in daily life, the performance requirements for servers are also getting higher and higher. In order to provide server performance, improving the performance of a single CPU node can no longer satisfy people's expectations for server performance. Therefore, it is necessary to increase the number of CPU ways in the server to improve performance. [0003] The server interconnect chip (CC chip) is the core chip of the multi-processor shared main memory system. Its main function is to maintain global cache consistency, and realize global IO sharing and system-wide interruption. In order to make the system have good practical performance...

AI Technical Summary

Problems solved by technology

[0005] In the chip FPGA prototype verification process, due to the increasing scale of chip design, it is impossible to transplant the entire design of the chip to a single FPGA chip. Therefore, it is relatively reasonable to cut the design and transplant it to each FPGA chip. It needs to be connected through a high-speed interface (such as Xilinx's Aurora high-speed interface), and in the debugging process, the handshake process of the high-speed interface between FPGA chips is easy to fail, so it is necessary to constantly reset the design or reload the FPGA bits. flow to reconnect the high-speed interfaces between FPGA chips, which brings great difficulty to debugging

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