Layout pattern for static random access memory

Abstract

A layout pattern of a static random access memory is disclosed and at least includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor and a second access transistor on a substrate; a plurality of fin structures disposed on the substrate and including at least one first fin structure and at least one second fin structure; a J-shaped gate structure including a long part, a short part and a bridge part connecting the long part and the short part; and at least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part.

Description

technical field [0001] The present invention relates to a static random access memory (static random access memory, SRAM), in particular to a layout pattern of the static random access memory (SRAM) with increased yield and improved reading speed. Background technique [0002] An embedded static random access memory (embedded static random access memory, embedded SRAM) includes a logic circuit and the static random access memory connected to the logic circuit. The SRAM itself is a volatile memory cell, that is, when the power supplied to the SRAM disappears, the stored data will be erased at the same time. Static random access memory stores data by using the conductive state of the transistor in the storage unit. The design of static random access memory is based on mutual coupling transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep data. Loss, that is, the action of not needing to update the memory, is different ...

AI Technical Summary

Problems solved by technology

[0003] However, with the reduction of manufacturing process line width and exposure pitch, it is difficult to use the existing structure to expose the desired pattern in the manufacture of SRAM components.

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