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Cache processing method and device

A technology of high-speed buffering and processing methods, applied in the computer field, to achieve the effect of improving Cache performance and reducing Cache storage overhead

Active Publication Date: 2017-10-24
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Embodiments of the present invention provide a cache memory processing method and device, which can solve the problem in the prior art that group associative caches may need to be replaced repeatedly when the cache is missing and the associated storage space is full, reducing the cache memory size. Storage overhead, improved Cache performance

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  • Cache processing method and device

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Embodiment Construction

[0104] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0105]It should be noted that the terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be understood that although terms first, second, etc. are used herein to describe message services or modules, these message services or modules should not be limited by these terms, and these terms are only used to distinguish each other. It should a...

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Abstract

The embodiment of the invention discloses a cache processing method and device. The method can comprise the following steps that: Cache receives a main memory address sent from a CPU (Central Processing Unit), wherein the main memory address comprises a Tag and an Index 1; and a Set1 corresponding to the Index1 is searched, and a Set2 corresponding to an Index2 is searched; and a matched Cache Line is searched in the Cache Line of the Set1 and the Set2. When the method is adopted, power consumption expenditures during Cache deficiency can be lowered, and Cache performance is improved.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a cache memory processing method and device. Background technique [0002] In the development of computer technology, in order to fill the huge gap in speed between the central processing unit (Central Processing Unit, CPU) and the main memory, a high-speed, small-capacity cache memory Cache is set between the CPU and the main memory. It is of great significance to improve the performance of the entire computer system, and it is almost an indispensable part. [0003] However, in the computer system structure, Cache is managed by block (Cache Block), and Cache and main memory are divided into blocks of the same size, and information is loaded into Cache in units of blocks. Correspondingly, the CPU's main memory address is divided into two parts: block address and block displacement. The address of the main memory block is used to find the position of the block in the Cache, an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0868G06F12/0893
CPCG06F12/0868G06F12/0893Y02D10/00
Inventor 李生程永波李涛
Owner HUAWEI TECH CO LTD
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