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Comma detection and word alignment method and system suitable for JESD204B protocol

A comma, protocol technology, applied in the field of high-speed serial interface chips, can solve problems such as difficulty in meeting rate requirements

Active Publication Date: 2017-07-07
重庆湃芯创智微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Comma detection and word alignment methods in the prior art, if the rate requirement of 12.5Gbps stipulated in the JESD204B protocol is to be met, the parallel 10-bit comma detection and word alignment module must be at least 1.25Ghz (12.5G / 10) clock rate To meet the timing requirements, it can be seen that it is difficult to meet the speed requirements without using advanced technology and full custom design

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  • Comma detection and word alignment method and system suitable for JESD204B protocol

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Embodiment Construction

[0033] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Embodiments of the present application provide a method for comma detection and word alignment applicable to the JESD204B protocol, the method comprising:

[0035] Using the first register and the second register to buffer the input N-bit data respectively; wherein, the N-bit data includes at least one complete comma detection code;

[0036] Taking out N-bit data from the first register, and shifting the taken-out N-bit data for a preset number of times, and obtaining an N-bit shift sequence after each shift;

[0037] Detecting the complete comma detection code in each of the shift sequences to determine the position information of the comma detection code;

[0038] After detecting the position information of the comma detection code, generate a shift address according to the state machine; the length of the shift address is the sam...

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Abstract

The invention discloses a comma detection and word alignment method and system suitable for a JESD204B protocol. The method comprises the following steps that: utilizing a first register and a second register to independently cache input N bits of data; taking N bits of data from the first register, carrying out preset-frequency shifting on the taken N bits of data, and obtaining a N-bit shifting sequence after shifting is carried out each time; detecting an integral comma detection code in each shifting sequence to determine the position information of the comma detection code; after the position information of the comma detection code is detected, generating a shifting address according to a state machine, wherein the length of the shifting address is the same with the length of the position information of the comma detection code; and according to the shifting address, carrying out shifting on 2N-bit data in the first register and the second register to obtain word alignment data. By use of the technical scheme provided by the invention, a 12.5Gbps rate requirement stipulated by the JESD204B protocol can be met.

Description

technical field [0001] The invention belongs to the technical field of high-speed serial interface chips, and relates to a comma detection and word alignment method and system applicable to the JESD204B protocol. Background technique [0002] With the continuous growth of people's demand for data volume, the traditional parallel IO interface technology has become a bottleneck problem for high-speed data transmission. As the high-speed interconnection of data converters and logic devices, the JESD204B interface protocol has great advantages in high-speed data transmission and simplified system design compared with traditional CMOS interfaces and LVDS interfaces. The JESD204B protocol is essentially a standard in serdes technology, which is mainly formulated for high-speed interconnection of data converters and logic devices. In the Serdes receiver part, the comma detection (comma detection) module is mainly used to indicate byte boundaries, obtain and verify byte synchroniza...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4068G06F13/4282G06F2213/0002
Inventor 唐枋李世平殷鹏陈卓叶楷舒洲王忠杰黄莎琳李明东夏迎军
Owner 重庆湃芯创智微电子有限公司
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