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Data window search method and circuit

A data window and query method technology, applied in the field of FPGA, can solve the problem that the LVDS interface cannot receive high-speed data correctly and stably

Active Publication Date: 2017-06-13
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a data window query method and circuit to solve the problem that the existing PLL-based data window query technology cannot realize the correct and stable reception of high-speed data by the LVDS interface

Method used

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  • Data window search method and circuit

Examples

Experimental program
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Effect test

no. 1 example

[0034] figure 2 The flow chart of the data window query method provided by the first embodiment of the present invention is composed of figure 2 It can be seen that, in this embodiment, the data window query method provided by the present invention includes the following steps:

[0035] S201: Convert the serial received data from the low-voltage differential signal interface into parallel data to obtain target data; based on the step of the current input and output delay unit, sample the target data to obtain the sampling result of the received data at the current step;

[0036] S202: According to the sampling result of the current step and the preset metastable state judgment parameters, judge and output the metastable state attribute of the current step, the effective state identification and the step position information, the metastable state attribute includes normal and metastable state; the step position is incremented by one, and output to the input and output delay ...

no. 2 example

[0043] image 3 A schematic structural diagram of the data window query circuit provided for the second embodiment of the present invention, by image 3 It can be seen that in this embodiment, the data window query circuit provided by the present invention includes:

[0044] The sampling circuit 31 is used to convert the serial received data from the low-voltage differential signal interface into parallel data to obtain the target data, based on the step of the current input and output delay unit, sample the target data to obtain the current step to the received data Sampling results;

[0045] The judging circuit 32 is used to judge and output the metastable property of the current step, the effective state identification and the step position information according to the sampling result of the current step and the preset metastable state judgment parameter. The metastable property includes Normal and metastable; the step position is incremented by one, and output to the inp...

no. 3 example

[0053] The present invention will be further explained in combination with specific application scenarios.

[0054] All current FPGAs have an IODELAY unit whose function is to adjust the delay of data circulating on the IO. The adjustment method can implement a fixed-value delay by setting fixed parameters, or dynamically adjust the data delay through the internal logic of the FPGA.

[0055] To solve the problem of low adjustment accuracy caused by adjusting the PLL phase, and to avoid sampling deviation caused by PLL jitter, this embodiment introduces a method of querying the data window by dynamically adjusting IODELAY. This method uses the sampling clock as a reference, and changes the sampling point by adjusting the phase of the data relative to the sampling clock. The adjustment range of this method is 128 steps, and the time width of each step is 25ps. If the data is transmitted at a rate of 700Mbps and in DDR mode, it is necessary to adjust 56 steps to traverse one bi...

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Abstract

The invention provides a data window search method and circuit. Delay adjustment is carried out on receiving data of an LVDS (Low Voltage Differential Signaling) interface by adjusting a delay parameter of an input / output delay unit; data window boundaries are found through the state of the receiving data; a sampling clock is taken as reference, and sampling points are changed by adjusting the phase of the data relative to the sampling clock; the adjustment precision is improved; a data window is relatively exquisite; and the sampling points are relatively abundant.

Description

technical field [0001] The invention relates to the field of FPGA (Field-Programmable GateArray, programmable logic device), in particular to a data window query method and circuit. Background technique [0002] Due to the high noise immunity and low power consumption of LVDS (Low Voltage Differential Signaling) technology, it has been widely used in the field of high-speed data transmission. The LVDS interface realizes high-speed data transmission and take over. Since the LVDS interface sends and receives serial data, it is necessary to train the received data to ensure that the receiving module can receive correct and stable data at any time. The process of training is the process of data window query. The data window is a collection of all sampling points that can collect stable data, and the center of the data window is the best sampling point. [0003] The existing common data window query method is realized by adjusting the phase of the PLL (PhaseLocked Loop, phase-l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/04H04L7/00
CPCH04L7/0033H04L7/04Y02D30/50
Inventor 龙鲤跃宣学雷
Owner SHENZHEN PANGO MICROSYST CO LTD
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