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B code time synchronization method based on VPX architecture

A B-code and architecture technology, applied to radio-controlled timers, instruments, digital transmission systems, etc., can solve the problems of low timing accuracy and out-of-synchronization

Inactive Publication Date: 2017-05-31
TIANJIN JINHANG COMP TECH RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is: under the VPX architecture, the time synchronization between multiple blades is not synchronized, and the time synchronization accuracy is low

Method used

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  • B code time synchronization method based on VPX architecture
  • B code time synchronization method based on VPX architecture
  • B code time synchronization method based on VPX architecture

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Embodiment Construction

[0018] Combine below figure 1 The block diagram of the VPX architecture shown, figure 2 The schematic block diagram of the PCIE switching network shown, image 3 The block diagram of the SRIO switching network shown and Figure 4 The schematic block diagram of the B code time synchronization method shown further describes the method of the present invention.

[0019] Such as figure 1 As shown, the VPX architecture consists of N blades, two switching boards, switching modules, and power boards. Among them, the blade provides computing resources for the system and realizes load balancing based on virtualization; the switching board can realize switching functions such as Ethernet, PCIE, and SRIO; the switching board can realize KVM switching; the power board configures different power supplies for each module. The management chip intelligently manages the power board.

[0020] Such as figure 2 As shown, the PCIE switch is realized by using a high-performance PCI-E switch...

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Abstract

The invention relates to a B code time synchronization method based on VPX architecture, and belongs to the technical field of accurate timing. The VPX architecture comprises a power board, an exchange board and a plurality of blade motherboards, and accurate synchronization and timing between blades are the premise of realizing the load balance of the system. Receiving and timekeeping circuits of a B code are implemented on an FPGA of the exchange board, and the FPGA can decode information indicating the second, minute, hour, date, month and year from the input B code. Meanwhile, the FPGA connects a PCIE interface to a PCIE switching chip of the exchange board, and the port is used as an EP. The CPU of the exchange board is used as a RC of a PCIE switching network, and the blades are set as an NT mode. When each NT (blade) requires time synchronization, the current time is required from the EP by an NT port of a PICE bus, and the extracted time is the system time after the time synchronization. Meanwhile, a serial RapidIO interface is reserved in the RPGA, and a RapidIO switch is used as redundancy backup of the B code system. By adoption of the B code time synchronization method, the time synchronization precision can reach a microsecond level, and thus has a very good application prospect in a VPX system.

Description

technical field [0001] The invention relates to the technical field of precise time synchronization, in particular to a B-code time synchronization method based on a VPX architecture. Background technique [0002] As an upgrade and replacement of the VME architecture, the VPX architecture has been favored by high-end applications such as military and aerospace once it was launched. The VPX architecture can support high-speed interconnection and serial switch structures, such as RapidIO, PCI Express, etc., and can meet the most demanding requirements of computer modules and digital signal processing modules. In the VPX architecture with high timing requirements, it is necessary to realize accurate synchronization and timing of multiple motherboards. The traditional time synchronization method is mostly at the device level. For board-level systems, the network time synchronization method is often used, but it is difficult to achieve synchronization, and the time synchronizati...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/00G04R40/00
CPCH04L7/00G04R40/00
Inventor 魏凯刘志杨柴营
Owner TIANJIN JINHANG COMP TECH RES INST
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