FPGA clock network design

Abstract

The invention puts forwards a scheme for FPGA clock network design for a programmable logic device. In order to meet the requirement for timing sequences by obtaining smaller clock skew, a design scheme for netted trees is adopted for the clock network. Clock burrs can be eliminated by filtration due to a push-pull structure added to a leaf unit. Noise interference caused by coupling and parasitic effect is eliminated so that stable waves are generated. In addition, configurable design is carried out on the clock network and is compatible to ordinary programmable devices.

Description

technical field [0001] With the continuous improvement of people's requirements for high-speed clocks, the design requirements of clock networks have become more and more stringent, and the quality of clock trees has become the key to the design of clock networks. This article introduces the basic concept of clock tree and gives a clock network design scheme in programmable logic devices. Balancing propagation delays through a clock tree results in less clock skew, which reduces its impact on setup and hold times. The push-pull structure is adopted in the leaf unit of the clock tree, which has the function of deburring, eliminates the interference of coupling noise, and ensures the reliability of the clock. In addition, the clock network of the device has programmable capability, has good flexibility, and is universal for general programmable logic devices. Background technique [0002] With the rapid development of the manufacturing process, the chip size is shrinking and...

AI Technical Summary

Problems solved by technology

In addition, the current circuit design is becoming more and more complex, and the design requirements for the clock are also getting higher and higher. In order to meet their own needs, the clock system is ever-changing

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