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Accelerated routing method

A wiring method and wiring technology, applied in the FPGA field, can solve problems such as wasting time

Active Publication Date: 2017-02-22
HERCULES MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the disadvantage of this method is that in the wiring process, if the net with large fanout and the net with small fanout are congested, it will not be determined in advance which net is the net with large fanout and which is the net with fanout. small wire mesh
In this way, a lot of time will be wasted

Method used

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Embodiment Construction

[0029] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0030] figure 1 A schematic flowchart 100 of a method for accelerating wiring provided by an embodiment of the present invention. As shown in Figure 1, the method includes:

[0031] Step 110, taking out the first net from the first-in-first-out queue according to the wiring sequence of all nets.

[0032] Specifically, the first net is taken out from the first-in-first-out queue according to the wiring sequence. It should be understood that the first net here does not specifically refer to the first net added to the queue in terms of order. Rather, it is the net whose routing order is prioritized relative to other nets contained in the current FIFO queue.

[0033] Optionally, before step 110, the method may actually include step 105, adding all wire nets to a first-in-first-out queue sequentially according to the wi...

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Abstract

The present invention discloses an accelerated routing method. The method comprises: removing a first net from a first-in-first-out queue in a routing order of all nets; when it is determined that the first net is congested and it is determined that a fan-out of the first net is greater than a first pre-determined threshold, determining whether a current iteration period is a special iteration period; when it is determined that the current iteration period is the special iteration period, disconnecting the first net and rewinding; when it is determined that the current iteration period is a non-special iteration period, determining whether the current first-in-first-out queue is an empty queue; when the current first-in-first-out queue is a non-empty queue, removing a second net from the current first-in-first-out queue, and repeatedly carrying out an iteration flow of the current iteration period; and when the current first-in-first-out queue is the empty queue, terminating the iteration flow of the current iteration period.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a method for accelerating wiring. Background technique [0002] In the traditional field-programmable gate array (Field-Programmable Gate Array, referred to as FPGA) wiring algorithm, due to the high fan-out line network. Fan-out refers to the number of subordinate modules directly called by the module. In FPGA, the high fan-out out, it refers to a functional module driving multiple functional modules. Because of the existence of high fan-out nets, it generally takes a lot of time to wire nets containing high fan-out. In order to save wiring time , a kind of Pathfinder algorithm is included in the prior art. Pathfinder is the most popular a kind of wiring algorithm at present, and its core idea is to allow the occurrence of crowding (that is, 2 or more than 2 wire nets occupy the same winding in the middle iterative process) Line resources), and finally eliminate congestion throug...

Claims

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Application Information

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IPC IPC(8): G06F17/10
CPCG06F17/10
Inventor 耿嘉樊平
Owner HERCULES MICROELECTRONICS CO LTD
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