Array substrate wiring structure, liquid crystal display panel and liquid crystal display

Abstract

The invention provides an array substrate wiring structure. Each wiring unit in the array substrate wiring structure comprises nine data lines, four gate lines and a transistor matrix; the first, fourth, sixth, seventh and ninth data lines have a first polarity; the second, third, fifth and eighth data line have a second polarity; a first row of transistors are located between the first gate line and the second gate line; a second row of transistors are located between the third gate line and the fourth gate line; the first and fourth gate lines and the data lines with the first polarity control the transistors in the first, seventh, eleventh and the thirteenth columns; the first and fourth gate lines and the data lines with the second polarity control the transistors in the second, fourth, eighth and fourteenth columns; the second and third gate lines and the data lines with the first polarity control the transistors in the sixth, tenth, twelfth and sixteenth columns; the second and third gate lines and the data lines with the second polarity control the transistors in the third, fifth, ninth and fifteenth columns; even gate lines are turned on successively after odd gate lines in the gate lines are turned on successively, so that the polarity of each corresponding pixel and the polarity of any adjacent pixel are opposite.

Description

technical field [0001] The invention relates to the display field, in particular to an array substrate wiring structure, a display panel and a liquid crystal display. Background technique [0002] In order to reduce the manufacturing cost of liquid crystal panel production, a kind of liquid crystal panel with HSD structure emerges as the times require. In this type of panel, the number of gate lines is doubled, and the number of data lines is halved, so as to reduce the number of chips driving the data lines and achieve the purpose of reducing costs. This HSD technology is used in LTPS. Since LTPS itself has a splitter design, one trace at the fan-out is divided into multiple data lines, and the pixel data lines are controlled by timing. This will further reduce the pin output terminals of the integrated chip, reduce the size of the integrated chip, and save costs. However, this will cause the polarities of multiple data lines under the control of any one fan-out line to b...

AI Technical Summary

Problems solved by technology

However, this will cause the polarities of multiple data lines under the control of any one fan-out line to be exactly the same, and the liquid crystal realizes the frame inversion mode during the polarity inversion process, which will cause severe flickering on the panel and affect Display panel performance

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